Hello all,
Regarding the TPS7A91 LDO:
According to the product's PDF, the minimum Cin/Cout is 10uF (page 4, section 6.3)
According to the TPS7A91 Evaluation board (TPS7A91EVM-831), Cin and Cout are P/N: GRM188R61C106MAALD (Murata)
if I take, for example Vin = 5V, and Vout = 3.3V, both capacitors have a actual capacitance (Under DC bias) far below 10uF
Is this fact taken for consideration?
Thanks!
Nir
Hi Nir,
As you mentioned, TPS7A91 requires a minimum 10 uF capacitor on the input and 10 uF capacitor on the output. You are also correct that application specific conditions will cause derating. As such the capacitance will be less than the capacitor value.
While the TPS7A91EVM-831 is a useful starting point for customers to evaluate their applications, we do not expect that the capacitors populated on the EVM will fulfill every application. Rather the EVM was designed with example capacitors as well as additional pads for customers to evaluate their own intended capacitors.
Very Respectfully,
Ryan
