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CCS/UCD3138A64: Implementation of timer interrupt

Part Number: UCD3138A64

Tool/software: Code Composer Studio

I tried implementing timer interrupt on ucd3138a64 , I made T24CMPCTRL0 register's bit 1 to 1 and used hardware interrupt of irq type but i am not getting any value on IRQIVEC . From the INTREQ register i can see that an interrupt is remaining to be serviced . How should i proceed in order to obtain a timer compare capture interrupt or a timer overflow interrupt 

  • Hello Anirudh,

    An engineer is looking into this and will get back to you.
  • It sounds to me like you haven't set the bit in the REQMASK register. That's the register in the Central Interrupt Module that enables the interrupts from the Timer 24 into the actual interrupt. Timer 24 actually gets 5 bits:

    #define CIMINT_ALL_TMR_COMP0 (0x00400000) // 22 24-bit Timer Compare 0 interrupt
    #define CIMINT_ALL_TMR_CAPT0 (0x00200000) // 21 24-bit Timer Capture 0 interrupt
    #define CIMINT_ALL_TMR_COMP1 (0x00100000) // 20 24-bit Timer Compare 1 interrupt
    #define CIMINT_ALL_TMR_CAPT1 (0x00080000) // 19 24-bit Timer Capture 1 interrupt
    #define CIMINT_ALL_TMR_OVFL (0x00040000) // 18 24-bit Timer counter overflow interrupt

    You can find the bit locations in the datasheet for each device - their functions change a bit on every device, depending on which peripherals are provided.

    Our training and EVM codes normally stay in user mode to provide a little protection, and the REQMASK can't be written to in user mode. So we use the software interrupt, with a function call called write_reqmask.

    So if you have this function, I think all you need to do is say:


    If you look at an EVM code, or, better yet, our training codes, you will see this function and how to use it.

    If you haven't checked out this videos and the codes, i suggest you try them. They are a good introduction to the UCD, the tools, and the code structure we use in our EVMs.