Other Parts Discussed in Thread: CSD19531Q5A,
Hello Team,
Could you help with our customer's question:
We are going to implement circuit from Figure 25 of datasheet(SNVS679B –NOVEMBER 2010–REVISED MARCH 2013).
What is the usage of D1? It will not save from the parasitic inductance of the wires as this described in Fig.22.
Also we cant understand the usage of D2.
As i know, In the case of a short circuit in the input power line while Q1 is not locked with an LM5050 chip will leak Reverse current. Parasitic inductance (output circuit) is charged by this reverse current, and at the moment of locking Q1 an emf of self-induction of parasitic inductance will be formed.
It will strive to keep the parasitic inductance constant. For this purpose, the authors of Datasheet propose to put a suppressor (aka Zener diode) D2 and limit this current by it
But in my opinion it is easier to put a ceramic capacitance parallel to the Cout electrolyte which is charged by the current stored in the parasitic inductance of the output circuit and will provide an output voltage rise of no more than 1V or even less, because the current in the parasitic inductance of the output circuit will depend on the time and speed of the locking of the transistor, and its growth rate will be determined by the same parasitic inductance of the energy will not be much.
The transistor we are going to use is CSD19531Q5A.
BR,
Ilya.
