UCC5390: h bridge UCC5390 design.

Hi Mohammad,

Thanks for the schematic.

I have couple of comments regarding your circuits:
-About the gate resistance I assume you are referring to the parallel combination of (R13 & R15) as well as (R14 & R16) on the turn-on path and the R23 and R25 on the turn-off path. The advantage from this current configuration may be the fact the external gate resistors will help dissipate power away from the driver. 4 resistors will have better power dissipation capability than a single gate resistance. It looks like you currently have 2.35-Ohms (equivalent resistance of R13 and R15) + 2.35-Ohms (equivalent resistance of R14 and R16) = 4.7-Ohms on the turn-on path (source current) and 2.35-Ohms (equivalent resistance of R23 and R25) on the turn-off path (sink current). Depending on your desired dv/dt at the gate, these values seem reasonable. Alternately depending on your switching frequency (high switching frequency = higher power dissipation within the driver), you may simply choose a single resistance with similar values to save component count and board space.

-With regards to the shorting resistance R17 at the input pins IN+/IN-? Keep in mind the inverting input IN– pulled high internally if left open and the non-inverting input IN+ pulled low internally if left floating. I noticed you mentioned that it is supposed to provide noise immunity in case of long PCB traces, however a small RC filter (Rin<100-Ohms and Cin< 300pF) at either input is generally sufficient to overcome noise on the input stage.

-You may want to reconsider the values of C23 and C21. 180uF seems excessive to me! I assume you want to get the full 10A drive current, please confirm. Low-ESR or ESL capacitors (4.7uF to 20uF at most) in parallel with C22 and C17 are generally sufficient to adequately bias the driver.
Additionally, keep in mind the total equivalent gate resistance will impact the drive current regardless how high you pick those bypass capacitors. The higher the impedance on the DRVout path, the lower the drive current (source/sink current) from the driver which will reduce the rise/fall times at the gate. On the flip side, the lower the impedance on the turn-on path, the higher the driver current and higher rise/fall times at the gate and the higher the risk of overshoot (resulting in EMI in your circuit).

Please let us know if you have further questions or press the green button if you have further questions.

Regards,

-Mamadou

Hi Mohammad,

It looks like your FETs have a total gate charge of only 17.3nC each which is really not a heavy load to cause full discharge from a 10uF cap (or to require 180uF). Our drivers have been biased with similar capacitance values to drive bigger loads/FETs so the point I am trying to make is that you really do not need that much capacitance. I have not tested our drivers with 180uF to confirm possible issues but you may continue so at your own risk.

In addition to previous comments, On the layout, I would recommend placing all the decoupling capacitors and clamp diodes as close as possible to the supply pins of the driver and shifting the FETs as close as possible to the driver to reduce PCB trace length and minimize parasitic inductance.

Other than, your schematic and layout look reasonable.

Please let us know if you run into trouble with your circuit or if you have further questions.
Meanwhile, if this addressed your concerns, please press the green button.

Regards,

-Mamadou

Hi Mohammad,

My apologies for the delayed response.

We have the simulation tools (unencrypted Pspice model) for this device available on the link below:
www.ti.com/.../toolssoftware

For each IC, you will require 2 separate power supplies, one for the primary side VCC1 and the second VCC2. Remember the driver is not sourcing/sinking 10A continuously, that is the peak current at a very specific time (very short duration, usually <1us) of the gate drive turn-on/off transitions.

Please let us know if you have further questions.

If not, please press the green button.

Regards,

-Mamadou