This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

CSD19532KTT: How to design the PCB layout so that the drain and sorce terminal can pass current as high as 50A at least?

Part Number: CSD19532KTT

Hello, TI community! Thans for your advice in advance.

I'm now designing pulsed power with CSD19532KTT (N-MOSFET, drian-to-source continue current 98A at 100 C). I want to parallel 10 CSD19532KTT to obtain high output current, say 500A or more, so each MOSFET need to pass 50A.

If I mount the MOSFETs on PCB board, the trace width must keep too wide to safely carry the high current. So, how should I design the PCB layout? OR

Is there any other solution to mount the paralleled MOSFETs, and ensure the current carry ability?

I searched for some resources but I still don't know how to realize it. 

Looking forward to your responding, and thanks very very much!