BQ24032A: STAT pin timing

Richard Friederich

Part Number: BQ24032A

What defines the time delay between CE going active (high) and the STAT1/2 pin(s) being pulled low? The chip is starting in its standby mode (AC present and PSEL high),

I have seen times ranging from ~15 to ~35 ms, but could it be even longer?

Is there any dependence of the delay on V(DPPM), RSET or R_TMR?

Is the delay specified anywhere?

over 4 years ago

0 Raheem over 4 years ago

TI__Mastermind 21590 points

Hello,
My lab measurement showed about 25ms. This number is governed by the deglitch time for recharge detection.

0 Richard Friederich over 4 years ago in reply to Raheem

Prodigy 240 points

Thank you, Raheem. I would not have expected that.

So, apart from dependence on DPPM, thermal regulation or precharge state, the delay is determined by the timer setting (I suppose that it's a fixed count of the timer oscillator). That gives me an potential option for controlling the time from CE to STAT1/2.

0 Raheem over 4 years ago in reply to Richard Friederich

TI__Mastermind 21590 points

Richard,
No, the deglitch time cannot be changed.

0 Richard Friederich over 4 years ago in reply to Raheem

Prodigy 240 points

Actually, I measure the time from CE assertion to STAT1 going active to be ~Rtmr * 0.4 ms/kΩ for Rtmr from 1 to 400 kΩ (far beyond the recommended range of Rtmr). This seems consistent with note (8) in the datasheet with regard to deglitch periods. For low battery voltages, the time from CE assertion to STAT2 going active is roughly double that plus 2 ms (although STAT2 also glitches active for about 100 µs when STAT1 changes state).

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BQ24032A: STAT pin timing