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TPS23757EVM: Regarding TPS23757 EVM schematis question

shermen fang
Prodigy 120 points
Part Number: TPS23757EVM
Other Parts Discussed in Thread: TPS23757,

Hi Sir,

In TPS23757 EVM schematic and datasheet, it shows there has gate1 for main NMOS switch and gate2 for senconary NMOS switch topology.

From datahseet, it shows gate1 and gate2 operation as below information.

GATE’s phase turns the main switch on when it transitions high, and OFF when it transitions low. GAT2’s phase
turns the second switch OFF when it transitions high, and on when it transitions low. Both switches should be
OFF when GAT2 is high and GATE is low. 

Many topologies that use secondary-side synchronous rectifiers also use N-Channel MOSFETs driven through a gate-drive transformer.
The proper signal phase for these rectifiers may be achieved by inverting the phasing of the secondary winding
(swapping the leads).

So, please help to provide  secondary-side synchronous rectifiers circuit design application note. Then we can understand and verify that

thanks

  • 0
    TI__Expert 3700 points
    Hi,

    Thank you for your question. Our team is currently out of the office celebrating the US holiday of Memorial Day and plan to be back in the office on Tuesday, 5/28. We will respond as soon as possible. Thank you for considering Texas Instruments PoE products.

    Best Regards,
    Brett
  • 0 in reply to Brett Colteaux
    TI__Mastermind 41470 points
    Hi Sherman,

    For synch rectifiers, you are right they can be a driven topology (gate drive transformer) or a self-driven (secondary gate winding). The topology selection is typically made by the efficiency spec.

    Unfortunately we don't have a specific app that goes into synch control design since it is a small part of the converter system. Rather its better to recommend a system PD solution with a TI design or EVM. Can you let us know your output voltage, output power , and efficiency spec?
  • 0 in reply to Darwin Fernandez
    Prodigy 120 points

    Hi Sir,

    1.Would you help to advise TPS23757 EVM synch rectifiers structure is driven topology (gate drive transformer) or a self-driven (secondary gate winding)?Which one is implemented?

    2.The output voltage is 12V and output power is for 802.3af application. It is refer to TPS23757 EVM design. Based on our internal test , the efficiency is around 84% , maybe has mesaurement error. Currently, we find TPS23757 datasheet hasn't describe more information regarding synch rectifiers circuit, would you have more reference documents or mesaurement report  that can explain it? Below picture is synch rectifiers control portion schematic, we'd like to know your design concept and critical point for measurement purpose, then we can follow your procedure for hardware design verification.

    thanks

  • 0 in reply to shermen fang
    TI__Mastermind 41470 points
    Hi Shermen,

    1. TPS23757 can be used in either topology. The TPS23757EVM uses a driven flyback converter.
    2. Efficiency for the 5V BOM of the TPS23757 EVM should be around 88% at full load and 84% at 0.75A. If you're getting 84% at full load, then it might be the test setup; you may want to measure the voltage directly at the output cap so the converter and not at the end of the load. Also, the voltage of the PoE input should be measured at the RJ45 (or maybe at the bob smith terminations) if it's difficult to get the voltage at the RJ45. This might be why the efficiency measurement is off. Are you measuring the EVM? or a copy of the EVM from your own board?
  • 0 in reply to Darwin Fernandez
    Prodigy 120 points
    Hi Sir,
    We'd like to know the synchronous rectifier control circuit component characteristic for Gate2 MOSFET in TPS23757EVM design.
    Would you have experience on how to select synchronous rectifier control circuit component and Gate2 MOS?
    thanks
  • 0 in reply to shermen fang
    TI__Mastermind 41470 points
    Unfortunately there is no design app note for this but at a high level C27 T3 and C23 removes the DC component of the gate waveform of GATE2. T3 provides isolation and the AC signal to pass through. D8 rectifies the gate signal of Q1 and clamps the negative voltage of the gate.
    R18 C22 D10 R18 and Q3 allows for fast turn ON/OFF of the gate of the FET.

    the synch FET selection is based from ~VIN/n + Vout. this is the minimum. There is usually ringing so majority of the time, the FET voltage selection will be oversized which is why 30V is used on the EVM.
  • 0 in reply to Darwin Fernandez
    Prodigy 120 points

    Hi Sir,

    As you mentioned " the synch FET  selection is based from ~VIN/n + Vout. this is the minimum."

    I don't fully understand its meaning, would you have more explain or have an example to describe that ?

    Take an example, POE 48 V input and  12V output,  what is "n" definition?

    please advise

    thanks

  • 0 in reply to shermen fang
    TI__Mastermind 41470 points
    Hi Shermen,

    n is the turns ratio of the transformer. When the FET is off, the DC voltage (which does not include the voltage ringing spike) is (VIN/turns ratio) + Vout.