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TPS65263-1Q1: Sync Operation using ROSC pin

Part Number: TPS65263-1Q1

Dear, Sir.

My customer is designing their system applying TPS65263-1Q1.

Now, they are having several question relating the usage of Sync operation.

They will use 450kHz or 480kHz as the external Sync signal.

Please give your advice.

1. GND clamping diode & AC coupling capacitor.

They will put the diode for negative voltage clamp & the capacitor for

reverse flow avoidance. Is there any concern or side-effect?

2. The Sync signal is provided from OEM's front-end unit, not theirs

The comment is described on the datasheet not to recommend, but they

need to require OEM to maintain the proper Sync signal for eliminating fSW drop to 100kHz.

Sorry to ask this kind of matter, but hoping to get your advice at this time.

I guess fSW 100kHz operation would be un-lock to lock duration on the internal PLL.

If so,

1) Frequency deviation(amount of shift)_? Hz,

2) Duty change_? %,  

3) Input signal amplitude_? V

4) No signal duration_? sec,

would be influenced for PLL enter to un-lock.

Please calrify those parameters if possile.

Best Regards,

H. Sakai

  • Hi, Sakai

    Some comments:

    1. Due to every pin's ESD has body diode, so the external clamping diode is not needed, it can be removed.

    And the 1kohm reistor also can be removed.

    I think there is no side effect.

    2. When sync signal disappears, IC don't know it, it needs some time to judge the sync signal is disppeared or down frequency to 200kHz, so IC needs to wait 10usec (100kHz) to swtich back to resistor mode, so Fsw dropping to 100kHz cannot be avoided, and this is not the unlock problem.

    Input signal amplitude should be >=2.5V and <=V7V.

  • Dear, Zhao-san.

    Thank you so much for all of your advice & teaching.

    Sorry to ask you again, but I would like to double confirm.

    Please help me one more time.

    1. I tried to described as below following your teaching.

      I wonder my understanding is correct?

    2. What is the meaning of " >=2.5V and <=V7V " on your comment?

    Best Regards,

    H. Sakai

  • Hi, Sakai

    1. Your understanding is correct.

    2. The Rosc is low voltage pin, so the input sync CLK signal amplitude should be smaller than V7V pin voltage(internal LDO output voltage), and in order to enter sync mode, the amplitude should be larger than 2.5V.

  • Dear, Zhao-san.
    Thank you so much for all of your advice & teaching.
    Sorry to disturb your job again, but please give your advice
    one more time.

    1. TI does not recommend to switch from external clock sync to resistor
    mode. If customer would accept the 100kHz operation as the
    descripribed on datasheet, is there the concern anything else?
    The device would be still functional?

    2. The 10us wait is activated when the sync signal disappear or the signal
    frequency down than 200kHz. Correct?

    Best Regards,
    H. Sakai
  • Hi, Sakai

    1. There is no other concens, IC keeps functional in frequency switch.
    2. Yes, correct.
  • Dear, Zhao-san.

    Sorry again & again. It will be the last question regarding this topic.
    Please give your advice.
    1. I wonder 10us Wait never happen under the resistor mode because it is
    the operation using internal signal?

    Best Regards,
    H. Sakai
  • Dear, Zhao-san.
    Sorry I forgot to write on.
    2. Is it possible to clarify min & max of 10us Wait?

    Best Regards,
    H. Sakai
  • Hi, Sakai

    1. 10us wait timer will start to work when external CLK =0, it can be guaranteed, don't worry.

    2. There is no variation data for 10us wait. Usually, it has +/- 20% ~ 30% variation.