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TINA/Spice/CSD88537ND: CSD88537ND high side & low side approximate power dissipation

SIDDHARTH MOHAN
Genius 3205 points
Part Number: CSD88537ND
Other Parts Discussed in Thread: TINA-TI, , DRV8307, TIDA-00472

Tool/software: TINA-TI or Spice Models

Hi All, 

can anyone please let me know the expected approximate power dissipation through high side & low side mosfets of CSD88537ND ? 

Especially what would be  the expected power dissipation through low side mosfet ideally ?

thank you 

  • 0
    TI__Mastermind 31845 points
    Hello Siddharth,
    Thank you for your interest in TI MOSFETs. I can provide power dissipation estimates for the CSD88537ND but will need to know more details about the application and conditions: buck converter or motor drive, input voltage range, switching frequency, output voltage and current and output inductor. For buck converter, you can also use this spreadsheet to estimate losses: www.ti.com/.../slpc015.
  • 0 in reply to John Wallace1
    Genius 3205 points
    thanks for the reply John,

    the application is for BLDC motor driver using TI’s DRV8307. You may not necessarily do actual measurements but can you let me know what will be approx.. power dissipation peak & rms for high side & low side mosfet per phase when the mosfets are driven by DRV8307 ?
  • 0 in reply to SIDDHARTH MOHAN
    TI__Mastermind 31845 points
    Hi Siddharth,
    For a BLDC application, the power loss in the FETs is mainly from conduction loss since the switching frequency is typically low (~20kHz). With the FETs configured in a half-bridge, you can assume one FET is always on (except for a short dead time). Therefore, the total conduction loss for the two FETs is Irms x Irms x rds(on). For rds(on) you need to take into account the VGS gate drive voltage and temperature of the device as both affect the resistance. Please see this blog for more information: e2e.ti.com/.../how-to-minimize-mosfet-conduction-loss-in-battery-powered-motor-drives
  • 0 in reply to John Wallace1
    Genius 3205 points
    thanks for the reply John, if i have sufficiently spaced apart clocks to drive the high side & low side fets (sufficient dead time) in that case there would not be any case where high side & low side mos turn on together. What is the major source of conduction through the low side mos if we assume that he load on resistive only or atleast no capacitance on the output junction of the high side & low side mos ?
  • 0 in reply to SIDDHARTH MOHAN
    TI__Mastermind 31845 points

    Hello Siddharth,

    I received a response back from my colleague:

    I don’t have a collateral showing the power loss calculation in MOSFETs for BLDC control. 

    One quick reference should be TIDA-00472. Section 4.2 of the design guide document shows the loss analysis for an IGBT based inverter. The document link is http://www.ti.com/lit/ug/tiduar7a/tiduar7a.pdf

    The document shows the RMS current in the IGBTs, which will be same even for FETs. However the designer has to use the same parameters to calculate the MOSFET conduction loss, switching loss and diode loss during dead time. Only point consider is each FET conducts for 1/3rd of total electrical period.

  • 0 in reply to John Wallace1
    Genius 3205 points

    Thanks for the reply John, is the power dissipation through the high side mosfet supposed to be equal to the power dissipation through the low side mosfet ??

  • 0 in reply to SIDDHARTH MOHAN
    TI__Guru 62720 points

    Siddharth,

    Since it is assumed that the power delivered to the load is from the power supply, through the HS FET, through the load, back through an LS FET, yes, it is assumed that the power dissipation is very close or the same.

    Regards,

    -Adam