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LMG1210: Layer stack and component requirements.

Part Number: LMG1210
Other Parts Discussed in Thread: TIDA-01634

I'm intending to use the LMG1210 to drive a full bridge with EPC2020 FETs as shown in the image below.

The datasheet mentions the need for a 4 layer board. Is this necessary for low power applications or is it possible to get away with a 2 layer board? Maximum power over load will be 36W (12V into 4 ohm) switching at 500kHz.

Additionally, is there any issues with this circuit? particularly in terms of the bootstrap cap and diode?


  • Hi Dylan,

    thanks for reaching out about LMG1210 and TIDA-01634!

    The datasheet recommends using a four layer board mainly for minimizing the inductance while switching the power loop at a high frequency. LMG1210 circuitry is mainly on the top layer and will not be affected much. When paralleling FETs the output traces need to be on different layers to keep the loops the same length in which the adjacent layer is used to reduce the trace inductance. (found in fig4 of )  

    If not using paralleled FETs only 2 layers is needed to route LMG1210. The layout example (found in fig12 can be seen with the return for the outputs of 1210 on the adjacent layer connected with microvias in the thermal pad to reduce gate loop inductance. If not using paralleled FETs 4 layers can still benefit the output power loop by allowing larger ground planes for better thermal performance as well as power traces for lower trace inductance.

    Added inductance in the power loop will slow things down with ringing however since the switching frequency is 500kHz the rise and fall times can be be 10's of ns with out affecting the operation. Worse case from not reducing the power loop inductance too much is ringing which causes dv/dt shoot through and may damage the FETs or driver. Following the layout in section 10 of the datasheet and section of the TIDA will help lower the power loop inductance to avoid this. For example reduce the switch node parasitic capacitance to help with Coss power loss by reducing the overlap between switch-node and power ground planes. Check out the altium design files for LMG1210 EVM  ( which is similar to the TIDA however does not parallel  FETs.

    Since EPC2020 has a similar gate capacitance to the FETs used in the TIDA and EVM the bootstrap cap and diode selection is ok. Place an additional cap on VCC (which is actually called VDD pin in the datasheet) of 100nF for high frequency filtering and peak drive current sourcing. Place the VDD cap and boot cap close to the device for the lowest inductance gate loop.

    let me know if this answer your question or you have any more questions!


  • Thanks Jeff for the detailed response!

    My current design (shown in the original post) will use two separate LMG1210s for each leg of a full bridge. There are no parallel FETs and layout is very similar to  Figure 21 in it currently uses 4 layers where the top layer is routing and the bottom three are ground. It seems this is unnecessary and the extra layers are recommended for return path of parallel FETs if used. I'll attach a picture of the layout below.

    Additionally, the FETs shown in TIDA-01634 have a gate charge of 0.37nC whereas the EPC2020s in my design have a gate charge of 16nC typ. Will this cause issues at 500kHz in regards to dead time? I.e will the EPC2020s with a gate charge of 16nC discharge in time allow the LMG1210 to provide a large enough dead time?



  • Thanks for the update Dylan,

    You are correct, the other 2 layers are mainly to help to  have large ground planes to spread out the heat or large return planes to create a low inductance loop.

    Since the LMG1210 rise and fall times are so short and the 500khz period is so long a 20ns dead-time will be no problem for LMG1210. The load current should be able to turn the GaN on in reverse fast enough before the low side turns on. You can also add some gate resistance to slow the low-side on time down to allow the switch node to commutate to compensate the short dead-time as well.

    Let me check out your layout and I will update you with some recommendations.


  • Hi Dylan,

    My name is Mamadou, I work with Jeff.

    We have not heard from you, we must assume that you have resolved the issue to this point. I will therefore mark this thread as resolved and close it. 

    Please let us know if you have further questions by posting on this thread.

    If you do not have additional questions, please also let us know by clicking the green button. 

    Thank you for your interest in our drivers.



  • Hi Jeff and/or Marmadou, sorry about the late reply.

    I'll attach the Schematic and PCB files and pictures below. I've kept the four layers to maximize ground loop performance.

    The PCB is unfinished and includes other components for the PWM modulator, feedback and integrator where R29 and R28 lead to the differential feedback opamp so you can ignore everything above R29 and R28.

    Let me know what you think about layout. Keep in mind i'll be hand soldering/flowing with heat gun this so it can't be *too* tight.

    Also, I completely separated the power ground from the rest of the circuit. Is this good practice?


    LMG1210 EVM

  • Hi Dylan,

    thanks for the detailed layout update, 

    To return the driver LO current path there needs to be a GND return just like there is on HS from HO.You want to be able to have separate power ground and driver ground but you cant separate them completely unless you have a kelvin connection  FET. For example pin2 (PGND) of your FET needs to have a return to driver ground to complete the LO path. This can be done by connecting the adjacent layer 2 ground plane together on either side. This will allow the low inductance return path. The HS return path can also have a HS plane to similarly return the path in a low inductance way. The HS and GND planes that the 1210 sits on can interact with the power loop. Check out the EVM altium design files and see how the 1210 thermal pads use the adjacent layer 2 to connect to the FETs sources. 

    The HB-HS boot cap is close to the device which is good however the POS_5V cap large and the return path is long. Choosing a smaller sized cap and allowing it to be closer to the pins as well as using ground vias to the adjacent ground plane will help with the LO loop.

    Also the GND plane on the bottom layer has no connection to the 1210 GND. (And mentioned before the HS has no plane to connect to). Also J1 and C1 POS_5V node do not connect.

    let me know if you need another review or have any other questions.


  • Hi Jeff, 

    Thanks for a really helpful reply,

    I've made the changes you suggested and ran a return path for HS as well as GND. I see what you mean about not seperating grounds for the driver and FETs. I assume there are other ways to keep power ground slightly separated from analog ground (Maybe using a very small resistance?) but I do not fully understand and have just created a common ground plane across the PCB.This ground plane will also interact with analog circuitry. Is this going to be okay considering the added decoupling caps on opamp supply rails?

    Additionally, just want to be sure that the supply for the LMG1210 is done right by bypassing the LDO and using the common 5V supply.

    Here's the updated PCB.

    0143.LMG1210 EVM


  • Hi Dylan,

    The updated files look much better, VIN can be tied to VDD if not using the LDO as you have it. 

    Keep signal and power ground separated with star point grounding (in which the GND of the driver is connected to the other circuit nodes such as source of power MOSFET and ground of PWM controller or opamps at one, single point) and preventing return path overlap. Overlapping or crossing the return paths of the noisy power switching circuits with the signal or analog return creates noise coupling - if this happens then use decoupling caps of different sizes close to the driver or opamp pins or the power supplies to filter the noise that returns. 

    Also consider the return paths to the power supply, Vias are needed to allow large ground plane areas to not just sink heat but allow the return signals to return in the shortest way. The current from the signal or power will want to find the path of least resistance which means the smallest loop area to return back to the source it came from. With a large ground plane, the return path through the ground plane will follow the signal trace path as closely as possible. The VIN power path supply of your lower half bridge may want some decoupling and bulk caps to maintain the same performance as the top half bridge which uses C3 and C7.

    let me know if this helps answer your question or you have any more.


  • Thanks Jeff for all your help, I appreciate it mate.