LMG1210: Layer stack and component requirements.

Hi Dylan,

thanks for reaching out about LMG1210 and TIDA-01634!

The datasheet recommends using a four layer board mainly for minimizing the inductance while switching the power loop at a high frequency. LMG1210 circuitry is mainly on the top layer and will not be affected much. When paralleling FETs the output traces need to be on different layers to keep the loops the same length in which the adjacent layer is used to reduce the trace inductance. (found in fig4 of )  

If not using paralleled FETs only 2 layers is needed to route LMG1210. The layout example (found in fig12 http://www.ti.com/lit/ds/symlink/lmg1210.pdf) can be seen with the return for the outputs of 1210 on the adjacent layer connected with microvias in the thermal pad to reduce gate loop inductance. If not using paralleled FETs 4 layers can still benefit the output power loop by allowing larger ground planes for better thermal performance as well as power traces for lower trace inductance.

Added inductance in the power loop will slow things down with ringing however since the switching frequency is 500kHz the rise and fall times can be be 10's of ns with out affecting the operation. Worse case from not reducing the power loop inductance too much is ringing which causes dv/dt shoot through and may damage the FETs or driver. Following the layout in section 10 of the datasheet and section 2.2.4.2 of the TIDA will help lower the power loop inductance to avoid this. For example reduce the switch node parasitic capacitance to help with Coss power loss by reducing the overlap between switch-node and power ground planes. Check out the altium design files for LMG1210 EVM  (http://www.ti.com/tool/LMG1210EVM-012) which is similar to the TIDA however does not parallel  FETs.

Since EPC2020 has a similar gate capacitance to the FETs used in the TIDA and EVM the bootstrap cap and diode selection is ok. Place an additional cap on VCC (which is actually called VDD pin in the datasheet) of 100nF for high frequency filtering and peak drive current sourcing. Place the VDD cap and boot cap close to the device for the lowest inductance gate loop.

let me know if this answer your question or you have any more questions!

thanks,

Hi Dylan,

My name is Mamadou, I work with Jeff.

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-Mamadou

Hi Dylan,

thanks for the detailed layout update, 

To return the driver LO current path there needs to be a GND return just like there is on HS from HO.You want to be able to have separate power ground and driver ground but you cant separate them completely unless you have a kelvin connection  FET. For example pin2 (PGND) of your FET needs to have a return to driver ground to complete the LO path. This can be done by connecting the adjacent layer 2 ground plane together on either side. This will allow the low inductance return path. The HS return path can also have a HS plane to similarly return the path in a low inductance way. The HS and GND planes that the 1210 sits on can interact with the power loop. Check out the EVM altium design files and see how the 1210 thermal pads use the adjacent layer 2 to connect to the FETs sources. 

The HB-HS boot cap is close to the device which is good however the POS_5V cap large and the return path is long. Choosing a smaller sized cap and allowing it to be closer to the pins as well as using ground vias to the adjacent ground plane will help with the LO loop.

Also the GND plane on the bottom layer has no connection to the 1210 GND. (And mentioned before the HS has no plane to connect to). Also J1 and C1 POS_5V node do not connect.

let me know if you need another review or have any other questions.

thanks,