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TINA/Spice/CSD18510KCS: Dynamic load design

Part Number: CSD18510KCS
Other Parts Discussed in Thread: TINA-TI, , OPA197, OPA2990

Tool/software: TINA-TI or Spice Models

Hello,

I am currently trying to design a dynamic load circuit, whose purpose is to drain a specified current from a voltage source (eg battery or a DC/DC converter).

In this purpose I am interested in the nMOSFET CSD18510KCS, which I consider using in that kind of topology :


The VREF voltage will be generated by a DAC controlled by a MCU, and the OpAmp will regulate the gate voltage of the transistor so that the voltage across the resistor will be the same as the reference voltage.

I have two questions :

Is the CSD18510KCS suitable for that kind of application (I will use a heat sink in order to optimize power dissipation) ?

I can't find the unencrypted PSPICE model or the TINA model on the website, does someone now where I can get them in order to simulate the circuit on TINA TI ?

Best regards,

Guillaume Levant

  • Guillaume,

    Thanks for your interest in our FETs.

    I spoke with our applications team and in principal the schematic should work. It showed the current is 3A but doesn't show the voltage so you will need to verify  SOA and power dissipation are within datasheet limits. In the schematic the opamp is in open loop mode so most likely the system won’t be stable, we suggest you add a compensation circuit to stabilize the system.

    As for a TINA or un-encrypted model, the fastest way to get you a model is un-encrypted. We do not post these on the web, I will send you a friend request to take care of this.

  • Chris,

    Thank you for your answer, indeed the maximum current I would like to be able to sink is 3A, but thanks to the DAC setting the reference, I would like to set a current as low as 1mA with the same circuit as well. For the voltage source, the minimum is 3V, and ideally the maximum would be 24V but in that case I am not expecting to be able to sink 3A. Since the MOSFET is in TO-220 package I consider plugging a heat sink to it in order to be able to dissipate as much power as possible.

    For the compensation loop I don't really know which kind of topology I need to implement. This is the first time I am designing that kind of circuit, so I don't really know where to start.

    Is this the kind of implementation you think about ?

    I guess once I choose the Opamp, some AC analyzis on TINA would help me to finetune this part.

    I accepted your friend request, thank you for your help !

    Best regards,

    Guillaume

  • Guillaume,

    Our apps support is now on vacation and will be back on monday, can you wait until then for a response on loop compensation?

  • Chris,

    Ok no problem I can wait until monday.

    Best regards,

    Guillaume

  • Hello Guillaume,

    There are many examples available on the web how to create a dynamic load using an op-amp and FET as the pass device. Below are a few links I found. If you have questions about the op-amp design and its compensation I can tie in our op-amp applications team. As Chris pointed out in his previous post, we want to make sure that the FET remains within the SOA and power dissipation limits as specified in the datasheet in your application. Please let me know what I can do to help you.

    http://www.ti.com/lit/an/sbva001/sbva001.pdf

    http://www.ko4bb.com/Test_Equipment/DynamicLoad/

    https://www.analog.com/media/en/technical-documentation/application-notes/an133f.pdf

  • Hello John,

    Yes I think I would need some guidance for the compensation loop design, is there anyone with who I can get in touch in order to get some help ?

    I looked into SOA in the datasheet of the transistor, and according to my understading of the following figure, it seems that I can sink DC current up to 3A safely as long as the VDS is under 20V, am I correct ?

    For power dissipation, I would like to sink at least 1A from a 24V load, so I have to dissipate 24W. Given the RJA of the CSD18510KCS (62°C/W), I can't do it without a heat sink.

    The ambient temperature will be around 25°C maximum, so the temperature rise must not be above 150°C. RJC being around 0.6°C/W and assuming the Case-to-Heat sink thermal resistance is about 0.4°C/W (I'm not sure how I can calculate this value accurately), the RJA of the heat sink should be below 150°C/24W - (0.6+0.4 °C/W) = 5.25°C/W, is it correct ?

    Please let me know if my understanding is correct, I am quite unexperienced on those aspects of SOA and power dissipation.

    Thank you so much for your help,

    Best regards,

    Guillaume Levant

  • Hi Guillaume,

    I took a closer look at the SOA curves and for the DC curve, with VDS = 24V, max IDS = 2.1A. Based on this, you should be OK with VDS = 24V & IDS = 1A from a SOA perspective with Tamb = 25degC.

    I would make one correction to your thermal impedance calculation. The maximum junction temperature for this device is 175degC. For reliability purposes, you probably want to derate this by at least 15degC which gives a maximum temperature rise above ambient of 175 - 25 - 15 = 135degC. I calculate the equivalent thermal impedance: Rtheta = 135degC/24W = 5.625degC/W. This would be the total thermal impedance from junction-to-case + case-to-heatsink (including a thermal grease or pad) + heatsink-to-ambient.

    We have some pretty good blogs:

  • Hi John,

    Thank you for these informations. I think I have everything I need for thermal dissipation calculation.

    Right now I'm looking into compensation loops now, I'm trying to find some documentation about it.

    Best regards,

    Guillaume Levant

  • Hi Guillaume,

    I am going to send this one to our op-amp apps team to help with the compensation part of it.

  • Hi Guillaume,

    The compensation used to stabilize the amplifier will be dependent on the op amp used. Do you have an op amp part number you are using for your design?

    I recommend taking a look at our TI Precision Lab videos on Stability for recommend compensation techniques, the theory of what causes instability, and how to simulate phase margin of amplifiers.

    Thank you,

    Tim Claycomb 

  • Hi Tim,

    Thank you for your help and for the link, I'll look into it.

    The main supply of my design will be 24V, so I am considering using the OPA197, which can be supplied with up to 36V :

    http://www.ti.com/product/OPA197

    Do you think it can be suitable for that application ?

    Best regards,

    Guillaume Levant

  • The device used will be dependent on the requirements of your design. Specifications you should consider are; supply voltage, bandwidth, accuracy (offset voltage, CMRR, PSRR, Aol, etc.), drift, and slew rate (if you are expecting large transients on the input).

    Does the OPA197 meet all your design requirements?

    Thank you,

    Tim Claycomb

  • Hi Tim,

    The OPA197 fits my requirements for this application, I don't need outstanding performance as the current I would sink will change quite slowly.

    I am watching the videos you sent me and I have a couple of questions concerning adapting these methods to my application.

    The circuit I am designing is the following :

    VG1 is the DAC output. I added a voltage divider in order to have a better accuracy since the current I'm sinking won't exceed 3A, and the DAC will be supplied in 3V.

    Also I added R2 and R3 in order not to exceed 20V on the Vgs of the PMOS, no matter what the OpAmp output is.

    Based on the videos I've seen, I mae this circuit for AC simulation :

    R6 is here to mimic R1 for the DC biasing of the circuit. I kept the output of the OpAmp connected to the MOSFET so that its gate capacitance can be taken in account for the simulation.

    VG1 is here to feed the feedback network for the AC simulation. But I'm not sure if it should feed the gate of the resistor as shown here or the gate of the MOSFET. But for this last option, I don't know how to both include in my simulation the effect of the capacitance of the MOSFET on the output of OpAmp.

    Do you know if my implementation is correct ?

    Best regards,

    Guilaume Levant

  • Hi Tim,

    For AC simulation, I am considering this circuit instead :

    Here the AC source drives the MOSFET, T1 is here just as a capacitive load for the OpAmp.

    Do you know which of these implementation are the most relevant for my design ?

    Best regards,

    Guillaume

  • Hi Guillaume,

    I recommend taking a look at "Low Voltage IR LED Driver Reference Design for Photoelectric Measurement Subsystems" for help in designing the circuit. The reference design is for IR LED driving but the design process and circuit is almost identical. The document provides everything you'll need to know on how to simulate this type of circuit and what components to include to stabilize the amplifier (also discussed in the video I provided in a previous post).

    I also recommend using the OPA2990 if you do not need the bandwidth and high accuracy the OPA197 offers. The OPA2990 is a lower cost lower bandwidth device.

    Thank you,

    Tim Claycomb

  • Hi Tim,

    Thank you so much for your help, indeed this reference design was very helpful to me. After a bunch of simulations I managed to improve the stability of the circuit, but I have one last question :

    On spice I have under certain conditions a phase margin of -294°. I know that I must not have a negative phase margin but the thing the phase margin is supposed to be between -180° and +180°, am I correct ?

    So I guess it is just the simulator that does weird calculations, but actually the phase margin of the circuit is 66°, is that right ?

    For the OPA2990, I would rather stay with the OP197 since its offset is way lower, and I would like to have a good accuracy for low currents sinking.

    Here is the design as it is now :

    Best regards,

    Guillaume

  • Hi Guillaume,

    For phase margin measurements you use the total phase shift. So it just depends on what the simulation uses as a starting phase. If it starts at -180 degrees its possible for it to go all the way down to -360 degrees for a total phase shift of 180 degrees.

    Thank you,

    Tim Claycomb

  • Hi Tim,

    Ok I understand, so all in all my circuit is stable now. Thank you so much for you help !

    Best regards,

    Guillaume