Hi there
we use 4~8 pcs of TPS54521 and other synchronized DC/DC， each powered 5V/5A. As required by system design, all DC/DC will be synchronized with external clock generated from FPGA.
Our questions is, can we use ONE clock to drive all there RT/CLK pins of DC/DC (routed in Daisy-Chain topology) ?
Since FPGA IO pin has limited driving capability around 4mA, and I found no info about RT/CLK pin's input resistance and capacitance in TPS54521 datasheet. There might be potential issue of distorted clocks signal when driving multiple loads (especially the capacitive loads). And I also not sure whether the would be any bad influence on Vout , such as larger jitter on clocks which may lead to larger output voltage ripple .
Plan B is to use a buffer IC to fanout independent clocks to feed each IC , but it is more cost and increase layout work.
Hope TI expert could provide insights for our concerns. Thanks.
