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TPS720: Output Regulation Failure on No-Load Condition

Part Number: TPS720


I have the following 1.8V power supply using the TPS720 (see schematics below):

  • It provides the MGTVCCAUX power domain for an Xilinx FPGA.
  • There is nothing on the output power domain except an additional 4.7uF decoupling cap.
  • Input voltage R3V3 is 3.3V
  • Bias R5 is 5V.

I am observing the following behaviour:

  • Under No-Load condition (FPGA is not yet mounted) the output slowly rises to 3.3V instead of staying at the target 1.8V.
  • If a <10kOhm resistor is connected as a load to ground, the LDO is able to regulate the output to the target 1.8V.

What is wrong with the way we are using the TPS720 such that it is not working as described in the datasheet under NO-LOAD condition?


  • Hi Pascal,

    From a schematic point of view your application is fine.  Generally when the output of a linear regulator is higher than the set voltage, it is due to an unintentional leakage path. Your description of a slow increase on the output supports the possibility of an unintentional leakage path.  When you add a load you are able to defeat this leakage path.  These paths can be from a variety of locations including residual flux that was not properly cleaned after assembling the PCB.

    Very Respectfully,


  • Thanks, Ryan!

    Your input was very helpful. The unintentional leakage path was through the diode, which we placed for additional safety for the power-off sequencing.
    Removing the diode solved the issue.

    Best, Pascal