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UCC27511A: How to use UCC27511A

Part Number: UCC27511A

Hi Team,

Please help me answer the follow question from my customer, thank you so much.

As I driven Nch MOS-FET with circuit like attached.
There was a problem that the output of UCC27511A was damaged.
The output pin is shorted to GND (about several ohms). It is a phenomenon that only SOURCE side, only SINK, both are short circuited.
The phenomenon has been improved by setting the GATE pull-down resistor, which is open in the circuit diagram, to 10kohm.
The same problem still occurs.
No problem has occurred up to now to change this resistance to 1K 2.2K, and 3.3Kohm, .

1) Mechanism of failure occurrence.
2) Notes on using UCC27511A.
3) Validity of the current treatment (insert 2.2 Kohm pull-down resistor with GATE).
4) Other appropriate using.

QTCE-0001.pdf

Best Regards,
Tom Liu

  • Hello Tom, 

    Thanks for your help promoting our drivers, my name is Mamadou Diallo from the High Power Drivers team.

    I have few comments/questions in order to get full background before commenting on possible root causes of the issue.

    What application is this for? Which IC on the schematic is the issue related to? Or do all ICs fail similarly? Does failure occur right at power ON or does it work for a certain time before failing? is there any damage to MOSFETs? Or just gate driver ICs having issues? 

    I also see "Negative" ground, "GND3", "GND2" and "GND1", "Output" and "VCC" can you please confirm values for these?

    5k to 10k gate to source resistance is usually adequate to prevent charge build up at the gate during off state. 

    From the schematic, it looks like each IC is driving 6 FETs in parallel in a non-inverting topology. Each FET has a total gate charge of 209nC at 10V Vgs. The combined load driven each IC is then 209nC*6= 1254nC. With that much load at the gate, I would first recommend reducing the external gate resistors as the maximum peak current seen at the gate is VDD/Rgate = 15V / 11-Ohms = 1.36A peak current well below the driver's capability. Assuming 0.5us (worst case) turn-on/off times requirements, the required peak current from the driver will then be: dQ/dt=C×dV/dt=Ipk=1.254uC/0.5us=2.5A. 

    Please change series gate resistance on OUTL to 0-3-Ohms and decrease series turn-on resistance on OUTH from 11 to 3 to 5-Ohms depending on desired rise times. 

    Thanks for the additional information. 

    Regards,

    -Mamadou

  • Hello Mamadou-san

    This application is switch of high current.

    These MOS-FETs switchs between "VCC" and "POSITIVE", "VCC" and "OUTPUT", "OUTPUT" and "NEGATIVE".
    Only GATE DRIVERs have broken. MOS-FETs have not any dameges.
    18page of datasheet
    • High dI/dt current from the driver output coupled with board layout parasitics can cause ground bounce. The
    differential voltage between input pins and GND is modified and triggers an unintended change of output
    state because of fast 13-ns propagation delay which can ultimately result in high-frequency oscillations that
    increase power dissipation and pose a risk of damage to the device.
    I think cause of my failuer is related  to abaove item.
    Best Regards,
  • Hello Tom, 

    Thanks for the additional information.

    That is certainly a possibility but I'd need more information to confirm/deny.

    Can you share (If possible) waveforms during "normal" conditions before the driver fails in order to verify whether ground bounce is a factor? 

    Additionally, please share PCB layout snippets to confirm or rule out parasitic effects from PCB traces.

    I'd also like to take a look at the input signal IN+ (directly at the driver's pin) OUT signal and VDD (for sanity check).

    Regards,

    -Mamadou

  • Hello Tom,

    I have not heard from you, I will therefore assume this issue is closed and mark this thread as resolved. If so, please press the green button or let us know if you have further questions by further posting on this thread.

    Regards,

    -Mamadou