Other Parts Discussed in Thread: TPS544C25, CSD87331Q3D, PMP12004-HE, TPS650861, CSD87350Q5D, CSD87588N,
Hi,
Part No.:- TPS6508640, TPS544C25,CSD87381P1, CSD87331Q3D
Evaluation Board:- PMP12004-HE
FPGA:- XCZU9EG-FFVB1156
i am using Xilinx "XCZU9EG-FFVB1156", for that trying to use "TPS6508640","TPS544C25" and PMP12004-HE
reference design. But reading the TI document getting few confusion. so requested to clarify the below point:-
1. As per Xilinx data sheet "VCCINT" should be powered up before "VCCBRAM", But as per TPS6508640 datasheet "VCCINT" getting
powered up later to "VCCBRAM". if we use the reference design as per TPS6508640, will it create any problem to FPGA while
power on and its functioning ?
2. please refer para 6.3 of "TPS6508640" datasheet saying that "Dashed lines show the option to short VCCINT with
VCCBRAM for cases where their voltages are the same and current < 25 A. In this case, the TPS544C25 device is not
needed and GPO1 should be shorted to CTL4". The suggested FET "CSD87381P1 (in TPS6508640 datasheet" " or "CSD87331Q3D (in PMP12004-HE)", having current rating max 15A.
then how to achieve the current requirement between ">20A and <25A" when "VCCINT" and "VCCBRAM" are shorted together.
3. as per xilinx dataseet (ug583, page no. 34, table no. 1-13), "VCC_PSPLL" power supply should be different then "VCC_PSAUX" power supply. but in "PMP12004-HE", both are
supplied by "BUCK 5". Also as per xilinx dataseet (ds925, page no. 4, table 2) recommanded voltage level for "VCC_PSPLL" is 1.2V while "VCC_PSAUX" is 1.8V, then
why both supply are coupled in "PMP12004-HE"?
4. Can we change the power sequence order in "TPS6508640" via I2C, permanentaly?
Thank You