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# Thermal data of TPS62125

Other Parts Discussed in Thread: TPS62125

We have a question about TPS62125.

We want to know the thermal data of allowable power dissipation about TPS62125.

Do you have the data?

Best regards,

Takahiro Nishizawa

• Hello Takahiro Nishizawa,

you can find detailed thermal information in the datasheet, section 6.4. You also can use WEBENCH for calculating losses and temperatures at your desired operating conditions.

Best regards,

Juergen

• Thank you for your support.

Our customer calculates Pd(allowable power dissipation).

Vin=6V

Vout=2.56V

Iout-0.1A

Pd=0.344

We want to know the derating of Pd.

Please show us the graph under the following condition.

Do you have the data?

We think that as the temperature(X) rises, the Pd(Y) goes down.

(Graph)

X : Ta(℃)

Y : Pd(W)

Please show us the Pd(allowable power dissipation) under the following condition if you don't have the graph.

Vin=6V

Vout=2.56V

Iout-0.1A

Pd=0.344

Ta=50℃

4-layer board

occupied area by copper foil : 6.28m㎡

Best regards,

Takahiro Nishizawa

• Hello Takahiro Nishizawa,

I don't understand what you try to calculate here.

If I just put in your data in webench I get an IC Pd of 24.16mW. This translates in a IC junction temperature increase of 1.58°C, calculated by webench as well. As you can read in the datasheet in the recommended operating conditions the device is specified to support maximum output power up to 125°C junction temperature, so there is no derating to be considered. Your design is not even close.

You can find a more detailed description in how to use the thermal parameters in the application note which is linked in the footnote below the table in section 6.4 in the datasheet.

Best regards,

Juergen

We have new questions about TPS62125.

We can find RΘja in datasheet p.4.

Please tell us the JEDEC condition of thermal information.

JEDEC high-k or  low-k?

JESD 51-7 or JESD 51-3?

How much does the value of thermal information change between high-K and Low-K?

High-K is 4-layer board and Low-k is 1-layer board.

Is this understanding correct?

Best regards,

Takahiro Nishizawa

• Hello Takahiro Nishizawa,

RΘja in the datasheet is defined for a JEDEC high-k board defined in JESD51-7. RΘja for a JEDEC low-k board defined in JESD51-3 is not available.

Please check the JEDEC standards for board geometry and layer stackup. JEDEC offers them on the web for download.

Best regards,

Juergen