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TPS732: LDO passing through input voltage unregulated when toggling enable

Marcus Müller
Prodigy 260 points
Part Number: TPS732

Hi!

I have an application where the TPS73225DBVR is fed with very instable input voltages, which could cause the LDO to be switched on and off successively with T<20ms. Vin and EN are tied together.

The first time the input voltage ramps to it's nominal voltage of 3.3V, the LDO outputs correctly its 2.5V as desired.However, with the following switching off and on of the LDO, the full 3.3V Vin is passed to the output for <5ms and then regulated correctly to the 2.5V again.

Do you know this behavior?

What workaround would you propose to prevent the output from exceeding the 2.5V?

Thanks a lot!

Marcus

  • 0
    TI__Mastermind 43610 points

    HI Marcus,

    The  NR/FB pin might not be discharging. If this pin still has charge from the previous power on cycle, the soft-start function will not work and can cause overshoot into the load. Seeing scope shots of the NR/FB pin, VIN, and VOUT would help to confirm this.

    If this is happening, some ideas to try could be:

    1. Lowering the 10nF capacitor to 1nf or 0.1nF.

    2. Increasing CIN

    3. Adding some resistance in series with VIN to help the input capacitor CIN work as a filter.

    I hope this helps.

    Regards,

  • 0
    TI__Mastermind 29180 points

    Hello Marcus,

    This type of issue can occur during brownout conditions when a linear regulator goes into dropout mode, briefly.
    I would recommend placing an antiparallel diode from the output to the input of the linear regulator.
    When the input to the linear shorts to GNDA, the output will also drop to approximately a diode drop above ground.

    Please let me know if this does not answer your question.

    Thanks,

    - Stephen

  • 0 in reply to JCHK
    Prodigy 50 points

    Hello John,

    I am the original questioner of this topic, thanks for your answers.

    Lowering NR/FB capacity or increasing CIN has no impact.

    Use an additional low pass will only shift the problem. 

    While the input voltage drops, there is still charge at the gate.

    I tried a voltage divider at the enable pin. This will work but in the data sheet only the enable voltage (>1,7V) is given.

    Is there a reliable threshold for disable?

    @Steven: The input voltage oscillate between 2V and 3,3V. No chance to short the output.

    Thanks, Tim

  • 0 in reply to Tim Labitzke
    TI__Mastermind 29180 points

    Hi Tim,

    In the TPS732 datasheet there is a shutdown specification, just below the enable voltage specification.
    To shut down the linear regulator, the voltage must be below 0.5V on the EN pin.

    If we have resolved your issue, please click the "Resolved" link at the bottom.
    If you need further assistance, please reply back and let us know.
    I will be monitoring this thread until it is closed.

    Thank you,

    - Stephen

  • 0 in reply to Stephen Ziel
    Prodigy 50 points

    Hi Stephen,

    I saw the threshold for the standby mode, but I thought there is a difference between standby (very low current consumption) and enable/disable the output.

    As I told, I clamped the EN-pin to a voltage divider (10k/15k) to get 2V@VIN=3,3V and 1V@VIN=1,65V. This works for my conditions and the EN-pin voltage never falls below 0,5V.

    Between 0,5V (standby) and 1,7V (enabled) is a large gap and I hoped, there is a reliable level to clear the internal gate source voltage.

    Thanks Tim

  • 0 in reply to Tim Labitzke
    TI__Mastermind 29180 points

    Hi Tim,

    You may be thinking of a UVLO type feature.
    For this device, there is only the enable / disable feature.
    A good description of this feature is provided in section 7.3.3 of the TPS732xx datasheet, copied below:

    If I have answered your question, please click the "Resolved" button below.

    Thanks,

    - Stephen

  • 0 in reply to Stephen Ziel
    Prodigy 50 points

    Hello Stephen,

    thanks for clarifying.

    I will select an other LDO.

    Thanks,

    Tim