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TPS54561-Q1: switch overshoot and high frequency switching noise

Part Number: TPS54561-Q1
Other Parts Discussed in Thread: TPS54561

TPS54561-Q1, input 22.4V, output 5.1V. Load is minimal <10mA. Design load is 4A. High side switch has very significant ringing, which is causing ~3Vpp noise on the input rail, and ~800mV oscillation on the outputs. In picture 2, you can see the overshoot is about 5 volts (peak vs high). The layout and schematic are shown below. I think I need to fix the layout, but I'm not sure what I could do to make the loop area smaller. The recommended layout is shown last. I know I have deviated slightly, but my inductor is also much larger than shown in the layout example. Is the problem that I put some of the components on the bottom side?

Happy to hear suggestions, thank you.

  • Hi Nick,

    The critical loop area for SW node voltage ringing is input cap -> high-side FET  -> freewheeling diode -> input cap. Reducing this loop area and placing a GND plane underneath the power stage are critical to minimize power loop parasitic inductance. Also, keep the SW node copper area to a minimum as this is a noisy node.

    However, I recommend reviewing the compensation values here -- C29 (6.8nF) that sets a pole for high-frequency noise attenuation should not he higher than C28 (1.8nF) that sets the compensator zero for phase lead before crossover.



  • Guess I shouldn't blindly trust the auto-generated web bench circuit. I still need to solve the switch ringing at no load before I get to the load response.

    High side loop is shown in green. Freewheeling loop shown in grey. Color loops are mapped on the schematic for reference. Freewheeling diode and output capacitors are on the bottom layer. I wonder if this is part of the problem.

    It seems that ground plane return currents will follow the layout patterns underneath the power components if you give them a chance. But the way I have constructed the circuit with the vias, that might be impossible. If I move the output capacitors to the right, and put vias in their ground pads, I think it will reduce the loop area.

    Does that make sense?

  • Hi Nick,

    The SW node ringing at no load is expected behavior -- this is the inductor resonating with the SW node capacitance when the inductor current reaches zero.

    Note there is only one critical loop comprising the input cap, MOSFET and diode. These are the components that carry high-frequency current. See more detail here:

    I recommend fixing the compensation by reducing the cap from COMP to GND (the pole frequency is too low now and contributes too much phase lag). See section of the TPS54561-Q1 datasheet.



  • What is scope plot #2 above -- is this the SW voltage? Also, can you provide a measurement of the output ripple as well.

    Note that the ripple will be somewhat higher at no load or light load as the converter operates in DCM.



  • Thank you for engaging with me. I really must get this right on the next board rev.

    Yes I will correct the incorrect compensation capacitance. That's a good idea. But I must first fix the very serious high frequency noise problem. Signal traces are below. Switch node is yellow 5V/div, input power is red 1V/div. Switch node ringing when the freewheeling current stops is ok. The 5V overshoot from the power loop inductance is not ok. My customer won't like 2-3Vpp 120MHz noise pervading through the whole system (see red). 

    I must reduce the circuit inductance with a board rev, but I am not confident that I know the correct thing to do, because I am not sure which loop is causing the problem. My theory is that the HSS circuit inductance is resonating against the freewheeling diode capacitance. D6 (FSV20100V schottky) diode has 500pF reverse bias junction capacitance at 20V. 1/(2*pi*sqrt(LC)) = 118MHz, L = 3.6nH. That's tiny, but then again so is my power switch loop! 

    Can you comment on my proposed layout changes below?

    • Move output caps directly under output pad of the inductor (helps if the oscillation is part of the inductor loop)
    • Put via stitching in gnd pad of output caps so return can flow where it needs to in the plane (helps if the oscillation is part of the inductor loop)
    • Reduce size of switch node, or make it an unfilled poly to reduce capacitance. (helps if the oscillation is in the power switch loop)
    • change to different diode with less capacitance (helps if the oscillation is in the power loop)
    • Put input capacitor right under the TPS54561, right next to the freewheeling diode (helps if the oscillation is in the power loop)
    • is there a better or additional change or something else I am missing?

  • Nick,

    The layout isn't that bad and some leading-edge switch voltage overshoot is generally inevitable. The lower-frequency ringing in DCM is the inductor resonating with the switch node effective capacitance. However, I think you're concerned with the power loop parasitic inductance that rings with the switch node capacitance when the FET turns on, i.e. the rising/leading edge of the SW node voltage.

    The leading-edge voltage overshoot and ringing (as well as the high slew rate, rising SW voltage) can couple to the output across the equivalent parasitic capacitance (EPC) of the inductor. My recommendation is to find an inductor with high self-resonant frequency (SRF), which effectively provides a low EPC for reduced noise coupling to the output. The Wurth inductor shown in the schematic has an SRF of 23MHz. Choose a smaller size inductor to achieve higher SRF and connect the dotted terminal (typically designates the inside of the winding) to the SW node so that the high dv/dt is shielded by the exterior of the winding connected to VOUT.

    Also, try using a low ESL cap, e.g. 10nF/0603, on the output. Finally, it is imperative to measure the output ripple directly across this using correct scope probe measurement techniques -- i.e. "probe and barrel" technique where the probe GND lead is removed, etc. to avoid high-frequency noise pickup.

    For the layout, you can also focus on reducing the copper area surrounding the inductor pad - this should be minimum area as it is a high dv/dt node and acts as a radiating surface.



  • The problem is definitely related to switch node parasitic capacitance. Previous diode had capacitance of 1500pF!! New, PDS5100-13 shottky diode has capacitance of 70pF at 25V input. This brought the overshoot down slightly and reduced the noise on the input bus from 2-3Vpp to less than 500mVpp.

    Second solution was adding a 10 ohm resistor in series with the bootstrap capacitor to slow down the gate. That added ~8ns to the rise time and cut the overshoot from 4V to 1V.

    The noise on the input bus has gone from 2-3Vpp down to ~200mVpp.

    Web-bench did not design in the 6.8nF high frequency compensation capacitor. It was supposed to be 6.8pF. My mistake was dragging in the wrong library part.