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LM5069EVM-627: startup waveform abnormal

Part Number: LM5069EVM-627
Other Parts Discussed in Thread: LM5069

Hi

My customer uses PSU with LM5069EVM-627, the second startup will abnormal, as below

What could be the reason?

There are currently actions is off UVLO, increst timer capacitor, add D2, R6..etc

  • Hi Bryan,

    What is the load at the output of LM5069EVM-627 ?

    Can you send me a test waveform including current information as well. Please include a image files for better readability. 

    In the test waveform please include

    • 48V input of isolated dc/dc converter
    • input voltage of LM5069EVM-627
    • output voltage of LM5069EVM-627
    • input current of LM5069EVM-627

    Thanks

    Rakesh

  • Hi Bryan,

    Can you provide test waveform to understand what's going on.

    Do you have 'Power Good' output from isolated dc/dc converter?

    BR,

    Rakesh

  • Hi Rakesh:

    test waveform as below.

    CH1: EVM input, CH2:EVM output, CH4:EVM input current

    PSU output capacitor is 2200us, 

    no power good funcition

  • Hi Bryan,

    Thank you. What is the source ? Is it from PSU.

    Are you seeing the similar behavior when tested from DC power supply.

    BR, Rakesh

  • Hi Rakesh:

    As the customer will EVM put behind PSU, operate in full load,

    when input switch from turn on to turn off,

    EVM input voltage couldn't put low, it still 15V,

    At this time PSU turn on input will see the phenomenon.

    PSU in load, not connect EVM, the action is normal, waveform as below.

  • Hi Bryan,

    Thank you. 

    Please do following two tests by making below changes on EVM.

    Test-1: Leave jumper JMP1 OPEN 

    Test-2: Configure the EVM as per Figure 4. Re-design the values of R1, R2, R3 and R4 to set UVLO at 23V and OVLO at 28V

    Also send me zoom-out waveform (above waveforms) in 1ms/div to see the behavior at the first instant

    BR, Rakesh

  • Hi Bryan,

    Did you see any change in the behavior with the above changes on the EVM ?

    BR, Rakesh

  • Hi Rakesh:

    No, I didn't.

    Recently customer add discharge circuit in EVM input, 

    speed up the discharge at the input

    It can improve this situation, input and output voltage can rise up smooth.

    Just curious why not discharge completely has this behavior.

  • Hi Bryan,

    When the input voltage drops near to UVLO threshold, LM5069 switches off the path and hence the input voltage stays there if there is no discharge path.

    BR, Rakesh

  • Hi Rakesh:

    Current set up of  way, indeed input drop to UVLO, the input voltage will stay there, 

    when the next turn on input, it should rise up smooth, actually not unstable,

    Is it possible that the range of hysteresis is not enough?

    UVLO keep EVM set  : Lower UVLO threshold is 17V

                                         Upper UVLO threshold is 18V

  • Hi Bryan,

    May be.. that's the reason I asked to check by shifting the UVLO thresholds

    Please do following two tests by making below changes on EVM.

    Test-1: Leave jumper JMP1 OPEN

    Test-2: Configure the EVM as per Figure 4. Re-design the values of R1, R2, R3 and R4 to set UVLO at 23V and OVLO at 28V

    Also send me zoom-out waveform (above waveforms) in 1ms/div to see the behavior at the first instant

    BR, Rakesh