UC1825A: UC1825A

Hey Jason,

As long as you stay within the 5 mA specification you will not damage the part.

I would be interested to see if there would be more changes to the switching frequency because of the loading over temperature and watch out for that, but I am unable to give you any more insight other than "watch out for this"

I'm unsure what plateau voltage you are worried about.

Could you elaborate?

Thanks,

Daniel

Hi Daniel,

A clock pulse frequency is 2.22us (450KHz), Pulse logic High is from 0V to 4V for duration of 200ns. When transition from Logh High 4V to Logic Low (should be 0V), it stays at 0.7V for 800ns and drop down to 0V after that. The 0.7V floating (plateau) is kind of a concern for what we use to drive a BJT.

Thanks

Jason

Hey Jason,

Is the CLK signal you are seeing not looking like Figure 3?

If not, can you try unloading the pin and seeing if that fixes it?

Thanks,

Daniel

Daniel,

I think you mean Figure 4 in the UC1825A datasheet. Yes it is slightly different. I have seen on another unit without loading, CLK signal is decay slowly like an RC time constant discharge circuit. I believe this circuit is loading with current and create a sharp drop to about 0.7V. I wonder if you could provide this Clock circuit schematic.

Regards,

Jason

Hey Jason,

Unfortunately I am unable to provide more detail than the block diagram in the datasheet due to NDA restrictions.

Thanks,

Daniel