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LMG1210: More info on sample layout in datasheet (Figure 10.2)

Part Number: LMG1210

We are investigating using the LMG1210 GaNFET gate driver for a high-frequency half-bridge power stage, and have reviewed two designs we found on the TI site (LMG1210EVM and TI Designs: TIDA-01634).

However, Figure 10.2 of the spec sheet for the LMG1210 driver has a detail of an example layout that does not seem to be from either of the above designs.  The figure shows a section of an interesting-looking board, but is incomplete and has very little explanation.

I am writing to ask if any more information about the layout in the figure is available?  In particular, can you provide the full layout? also a BOM?  Interestingly, the figure shows a peculiar foil pattern that looks like a millimeter wave low-pass filter - any explanation of that would be great as well.


- Patrick

  • Hi, Patrick,

    Thanks for your interest in our LMG1210.

    The foil pattern isn't for RF, it's to match the footprint for the EPC GaNFET on the PCB.

    Our office is closed for the Labor Day holiday, but my colleague will get back to you on Tuesday about getting more information on the info in the data sheet.

  • Hi Patrick,

    Thanks for reaching out about LMG1210. I think Don's right the pattern is coming from the footprint of the EPC GaN FET, this is their package design to lower the FET package inductance.

    The 10.2 layout figure in the datasheet was made as an example layout. The LMG1210 TIDA layout and EVM are more representative layout representation proven with test results and design files. I recommend to check out the EVM layout since its most similar to figure 10.2. Let me know if you have any other questions with LMG1210 layout.