For same circuit making two set power stage and get different PFC output DC Level, one is DC395V and another is DC406V,How can this situation be improved ?
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Thank you for your interest in the UCC28063A interleaved TM-PFC controller.
Consider that one output is -5V from 400V and the other is +6V from 400V, this can be thought of as 400V +/-1.25%.
Consider further that the controller regulation voltage VSENSEreg is specified as 6.00V +/- 0.15V at Ta = 25C (see datasheet), which is +/- 2.5% accuracy. Even further, the VSENSE feedback resistors each can have a nominal accuracy of +/-1%.
So achieving +/-1.25% repeatability where the nominal variation (not counting temperature and aging effects) may amount to +/-3.5% is relatively quite good. Since the IC accuracy cannot be changed, the only external options are to use 0.1% accurate resistors to improve the variation limits by about 1%.
Because the VSENSE resistors are usually of quite high value (several meg-ohms), be sure to keep the board clean of flux residue and other hygroscopic material (dust, grime, etc) that may form a leakage path from the high voltage output to the VSENSE pin and alter the feedback voltage.
I suggest to try to find where the main inaccuracy comes from. As I mentioned earlier, the IC cannot be changed (redesigned), so there is nothing that can be done to improve that. But I suggest to use an accurate, precise volt meter and measure VREF on each board (IC pin-15 VREF to pin-6 AGND) and see how much difference there is in reference voltages. Using 6.000V as the nominal, you can calculate the deviation for each IC. If this amounts to most of the percent deviation of the output voltages, then the IC is to blame.
But if the VREF deviations are a small part of the total % deviation of Vout, then some other aspect of the design must account for the difference (such as sense resistor tolerances and/or surface leakage due to moisture absorption).
Ideally, the voltage at VSENSE (pin-2 to AGND) should be equal to VREF except for a few millivolts offset. But probing VSENSE with voltmeter leads may introduce noise which could interfere with PFC operation. Be careful, if you do try to probe VSENSE, that you keep the meter leads twisted to minimum noise pickup (loop area) and keep them away from high voltage or high current switching noise sources.