UCC28061: UCC28061 harmonics issue in high line & Pin 75W

Hello Red,

In the UCC28061 (and -060 and -063/A), the TSET resistor programs the maximum on-time proportionately to its value.  In other words higher R allows longer on-time and lower R reduces maximum on-time. 

The COMP voltage modulates the cycle-by-cycle on-time partly influenced by power level and partly by input voltage.  In the case of high line and (presumably) light load, the on times should be short.  Since the loop bandwidth is very low, the COMP voltage is usually quite flat, so the on-times are constant across the line period.  However, at the low voltages around the line zero-crossings the current cannot build up sufficiently with short on-times, so the UCC2806x implements a zero-crossing distortion reduction feature which increases the on-time according to Figure 23 of the datasheet. 

Now, at high-line and light load, COMP voltage is very close to the error-amp cut-off offset voltage of 0.125V.   It needs to drop to a voltage level that provides the average power output spread out over the line cycle.  When TSET is a high value, COMP has to drop closer to the 0.125V threshold to get the low on-time necessary to regulate.  At this low level, offsets and disturbances have a greater influence on the harmonic content of each half-cycle.

When TSET is a lower value, it already programs a lower maximum on-time, so COMP does not have to drop as close to 0.125V to regulate.  In this case, the offsets and distortions have less effect on the cycle-by-cycle on-times so distortion is less.

(A similar situation occurs when dropping a phase, using the PHB input.  At light load, if both phases are operating, the on-times need to be very short.  But if phase B is disabled (PHB < 0.8V), the remaining phase has to provide all the power so its on-times need to be longer, and COMP voltage goes up to achieve that.  Then the offsets and distortions on COMP are less compared tot he 0.125V threshold and harmonic content is reduced.)

The side effect of reduced TSET resistance is that full power will not be supported with that value.  So assuming that an external circuit will switch in or out a parallel resistor on TSET (with suitable hysteresis), be careful to absolutely minimize any capacitance added to the TSET node.  TSET is sensitive to capacitance since the TSET function mirrors resistor current into a timing circuit.  Any noise currents capacitively-coupled into TSET will be mirrored into the on-time timing and directly affect cycle-by-cycle on time.     Since this involves uA level currents, it takes surprisingly little capacitance (even to GND!) to generate more than a few uA of noise current.  Keep any switching signals well away from any such TSET adjustment circuit.

I hope this answers your customers questions and concerns. 

Regards,
Ulrich  

Hi Red,

Tolerance of the Kt factor is shown in the spec table on page 6 of the released datasheet. 

Since you posted snippets of a "draft" spec, I suspect that it does not have min or max populated.  I suggest that you download the latest version from the TI website.  

By the way, on my previous reply I forgot to mention (for completeness) that the UCC28064A has a different response to TSET resistance.  Instead of on-time being proportional to Rtset, on-time is roughly inversely proportional.  In other words, as Rtset goes up, maximum on-time goes down, and vice-versa.  (This change is due to the way that input voltage feed-forward modifies the on-time algorithm. COMP becomes independent of Vin.)   But the same concern for side-effect remains: avoid introducing any capacitance on the TSET node whether adding an adjustment circuit or not.

Regards,
Uli