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TPS28225: EMC behavior

Elieser Mach
Prodigy 10 points
Part Number: TPS28225

Hi,

I'm having trouble passing EMC with this FET driver.

The design is for a wireless charger, operating in full-bridge topology using DMT3020 dual FETs.
Operating frequency range is 100-140[kHz.].

It seems as if resistors are required from the driver to the gate of the FET. The values of these resistors are quite high (>20[ohm]). Any way to reduce this value?

Still, there are noises in the following ranges: 20+-5[MHz.], 35+-5[MHz.] & 100+-5[MHz.].

Are there any specific guidelines \ ideas \ tips as to the layout (other than keeping short traces and the usual...)?

Any tips how to reduce emission generated by this driver? I realize that the rest of the circuit is probably radiating as well, but it seems as if the source is coming from the switching done by the driver.

Thanks,

Elieser

  • 0
    TI__Mastermind 20950 points

    Hello Elieser,

    Thank you for the interest in the TPS28225. It sounds like the application is functional as you require but there are EMI concerns. The general layout guidelines are as you imply which is recommended practice for laying out the driver and power stage. I will mention some of what may be obvious to you but include some considerations on the power train. Since this is a wireless charger, I would expect that excessive ringing on the half bridge power stage switch node will be a big concern since this is driving a large physical area coil.

    General guidelines: Keep the driver output to MOSFET gate, and MOSFET source to driver ground reference traces short length to reduce parasitic inductance. Place the VDD and boot capacitors close to the IC pins. Ensure that the driver input signal does not cross high dV/dt traces to reduce induced noise.

    For the power train: Keep the half bridge power train loop short from the input filter capacitance to the high side FET drain, high side drain to low side source, and low side source to the input capacitance negative terminal. Placing high frequency ceramic capacitors very close to the MOSFET half bridge can reduce the parasitic inductance of the power train switching loop. This can help reduce switch node voltage overshoot and ringing.  For the switch node trace, avoid overlapping the power train switch node trace with ground or the input voltage traces to reduce the parasitic capacitance. Some overlapping is unavoidable in many cases, but minimize the area of the overlap.

    Power train MOSFET selection: If the MOSFET half bridge power train will have current conduction during the MOSFET dead times, both MOSFET's off, there will be current conduction in the MOSFET body diodes. Select MOSFET with low body diode trr, or reverse recovery times. If you can find a device that has low trr and claims "soft recovery" characteristics this will be beneficial as well. Long body diode recovery times results in high dI/dt in the power train traces while the body diode is turning off. This can result in high voltage spikes and ringing on the switch node.

    Snubbing the switch node: Even with good layout and device selection, the switch node voltage spikes and ringing can be reduced considerably but still exists. If the EMI performance is sensitive to switch node ringing, as I suspect, it is a good idea to consider adding a snubber network to the half bridge.

    Advice on snubber circuit design can be found here. https://e2e.ti.com/blogs_/b/powerhouse/archive/2016/05/05/calculate-an-r-c-snubber-in-seven-steps?keyMatch=snubber&tisearch=Search-EN-Everything

    Advice on layout can be found in this reference design for a half bridge power train. http://www.ti.com/tool/TIDA-050022

    Confirm if this addresses your questions, or you can post additional questions on this thread.