UCC28950: Should I decouple the DCM pin with a 0.001uF cap ?

Hello Marc

It's difficult to diagnose what the problem is in your specific case but you are correct that if the SR is turned off when the current is back-feeding through it you will see a significant voltage spike on the SR which will avalanche it and which may destroy it.

One diagnostic tool that is sometimes useful is to disable the SRs and use their body diodes for rectification while you search for the cause of the problem. Simply remove their gate drive resistor and tie their gates to their sources.

If you are using paralleled MOSFETs for your SRs then please make sure you have separate gate drive resistors for each device.

I think that adding a capacitor at DCM won't cause any problems but I'm not sure if it will cure the problem either.

You should try using the UCC28951 device instead of the UCC28950. The UCC28951 is a 100% compatible device and you can simply remove the UCC28950 and replace it with the UCC28951 - no changes to schematic or component values are needed. The UCC28951 operates better at wide duty cycles while in current limit http://www.ti.com/lit/an/slua853/slua853.pdf

We have seen that adding a 20us time constant (C to GND) to the ADELEF pin helps suppress some switching glitches in one application.

Please review your PCB layout to confirm that none of the OUTx or SYNC lines run under the IC body.

If you can send or post some waveforms that would be helpful. Vds on the SRs during the transient and details of the transient would be especially useful. If you can't post them here then send them to me confidentially - I'm at

colingillmor@ti.com

Please let me know how you get on.
Regards

Colin

Hi Colin...

I think you misunderstood just a little.  The 0.001uF cap is already in the design.  I am considering reducing the value or removing it altogether because it may be causing the problem we have seen.

Unfortunately, I have no waveforms of the failure.  I have so far been unable reproduce it in the lab.  There are waveforms we took during design validation, yet there's no shoot-through or backfeeding in any of them.

There is anecdotal evidence that the failures occurred while transitioning from a high-load to a low-load state (as the supercap equalized with the output voltage).  However, this is impossible to confirm, as no automated monitoring was taking place.  I am trying to get a supercap in an effort to recreate the failure mode under observation.

In the meantime...can you tell me if adding a capacitor across the DCM resistor (220nS time constant) could be the culprit ?

Thanks !

Hi Marc

I can't say for definite but I doubt that a 220ns time constant could be the root cause of the issue. The system waits for 2 falling edges before making the transition from CCM to DCM - see the DS extract below.  I cannot be certain of this but I doubt that a small amount of noise filtering on the DCM pin would have much effect.

If you transition from high load to low load really fast then it is possible that the output inductor current could go negative during the 2 cycle wait state so this is where I suggest you look. Without knowing exactly what is going on it's not really possible to suggest a solution but things to consider would be

Reducing the load transient rate

Increasing the DCM threshold

Adding some TVS devices to absorb the avalanche energy at a safe voltage

Increasing the value of the output inductor

It may also be worthwhile checking some other operation corners -

The low to high load transition

Operation when the input power fails at high loads (this can put the controller in the Dmax/Ilimit condition)

Regards

Colin

Hi Marc,

It has been a week since Colin's last response, I hope that you have made some progress on the issue in the meantime. I am going to close the post and please open a new post if you have more questions.

Regards

Peter