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TPS549B22: Output and Input CAP check

Julian Chen
Expert 2550 points
Part Number: TPS549B22

Hi E2E,

Because we want to less layout area, could you check block 1~3 and let us know the minimum cap  demanded!

Thanks!

VDD0V8(0.8V)

TPS549B22RVFR

Vin=12V, Vout=0.8V, IOUT=15.1A

DC ripple SPEC is +/- 3%, Transient SPEC is +/-7.5%.

  • 0
    TI__Genius 14455 points

    Hi Julian,

       For the transient spec, can you please let us know what is the current step size in Amps?


    Also, did you use WEBENCH to create the design for this device? It will help us review the design if it was created in WEBENCH.

    regards,

    Gerold

  • 0
    TI__Mastermind 48160 points

    Julian,

    Given the fast response of the D-CAP3 control architecture in the TPS549B22, the limiting concern for the output capacitors would be absorbing the excess current in the inductor during a load release.

    With a 0.8V output and 470nH inductor, the negative slew-rate will be 0.8V / 470nH = 1.7A/us

    For a 15A to 0A load release, it will take 15A / 1.7A/us = 8.8125us for the inductor current to decay for zero, during which time the inductor current will deliver an average of 15/2 = 7.5A.

    7.5A for 8.8125us = 66.1uC of excess charge in the output capacitors.

    For input capacitance, you'll need enough ceramic input capacitors to handle the RMS ripple current and enough capacitance to limit the PVIN ripple to less than 250mV.  In order to calculate that, we'd need to know the switching frequency and input voltage of the converter.

    Each switching cycle, the high-side FET will draw IOUT (15A) from the input for 1.1 * VOUT/VIN * 1/Fsw (Duty-Cycle divided by efficiency, time switching period) from the input capacitors.  You need Cin > IOUT * 1.1 * (VIN/VOUT) * (1/Fsw) * (1 / Vin_ripple) to keep the input voltage ripple less than Vin_ripple.

    Allowing 7.5% of 0.8V for overshoot is 60mV.

    66.1uC / 0.060V = 1,101uF of output capacitance, after derating the output capacitors for DC bias voltage, tolerance, and temperature.

    Accounting for 20% capacitance loss and 20% tolerance, that requires 1,542uF