UCC28702: UCC28702

Hello Ramgopal, 

I'll try to help you debug this issue.  Looking back your previous E2E thread correspondence with Eric, I saw in your schematic diagram that the primary MOSFET is SPW11N80C3 and the output for this converter is 5V /1A.  The the 5-W power level the SPW11N80C3 is greatly over-sized. 

Although it may appear to work, I think the extremely high Coss may be the cause of this problem. 

Waveforms of the output (and other signals) would be a big help, but since none are available, my guess is that the huge Coss is causing a long turn-off delay, which in turn causes excessive peak primary current, which in turn drives the switching frequency much lower than expected for regulation.  At loads less than ~150mA, I think the controller cannot reduce the frequency low enough to regulate and the output goes into an over-voltage condition. The controller detects this OV and shuts down the switching.   Then it recycles start-up and runs up into OVP again, and repeats.  Meanwhile the light-load condition does not pull down the output voltage much below 4V before the next restart cycle happens, so the output fluctuates between ~4V and ~5V as you describe.  This is less likely to happen at lower voltages because the peak current is not driven as high during the turn-off delay and the frequency stays within the controller's capability. 

I recommend that you change to a much smaller MOSFET.  
In this design review document  page 11 indicates that a 4.5ohm MOSFET was used  at this power level.  I suggest to find an 800-V device with on-resistance around 4~5 ohms. 

With a much shorter turn-off delay, the controller can keep control over the peak current and should be able to regulate down to almost 0A.  Since there is a minimum switching frequency, you will need a minimum load, and I see in the schematic that you do have a "pre-load" of 124ohm = 40mA minimum load.  This is rather high, and after changing the MOSFET, you may be able to reduce this pre-load considerably as well.  

Regards,
Ulrich

Hello Ramgopal, 

Thank you for the additional information.  I entered your design values into the UCC28700 Design Calculator ( ) and it recommended some significantly different values for 2 of your components: R103 and R95. 

I recommend to:

a) change R103 from 6.98K to 840ohm (or closest standard value to 840R, +/-),

b) change R95 from 487R to 65R (or less, not more). 

I believe that item (a) is most likely to solve your light-load operating issue at high line.  The existing 6.98K is injecting far too much high-line offset to the CS input and making it difficult for the controller to achieve the proper peak current needed at high line. 

Item (b) is not yet an apparent problem, but the existing value could add a voltage spike to Vds far in excess of the 600-V rating of the new MOSFET.  With less than 65R at this location, the 600-V rated MOSFET should have decent margin to its max Vds rating. 
However, the calculator assumes that a fixed TVS voltage clamp is being used.  Since you are using an RCD clamp instead (which is perfectly fine to do), make sure that the clamp cap value at C37 is high enough to maintain sufficient margin to the MOSFET max rating at max output load and max input line. 

Please let me know if the light-load high-line operation problem is solved.  (Note: If so, you may investigate increasing R98 as well to reduce Pstby.)

Regards,
Ulrich

Hello Ramgopal,

I'm glad the previous problem was resolved. This new issue I believe originates from operation around the lower AM/FM transition point of the UCC28702 Control Law (see page 14 of datasheet).  Here, the lower loads are firmly down the Lower FM curve, and the higher loads are firmly up into the AM region, but the 50mA load seems to be very close to the transition point between the two operating modes.

Apparently perturbations in the waveform sensing at the VS input are confusing the controller somewhat and it can't decide whether to be in the AM or FM region and settle to a steady state. Instead it is overshooting first one way, then over compensating to the other way and back and forth.  Since there are no external components for stability, only increasing the output capacitance can reduce or eliminate this effect if the output ripple is unacceptable.  The ripple on VDD is of no concern or consequence.  Make sure that any capacitance at the VS pin is minimized as much as possible.

Regards,
Ulrich