I have a 67 % DC square wave, 1 Mhz, wich i want this TPSxx to syncronize to. This is exactly the switch node voltage of another buck, cascaded on the out of CH1 of TPS65263-1Q1.
Datasheet explains that:
-the active sync edge for TPS is the falling one.
-CH1 is 180° w respect to other channels
-on page 22 the period "....At the end of every clock cycle, the low-side MOSFET sourcing current is compared to the internally set low-side sourcing current limit. ...." enforces the idea that the transition to 'ON' state will take place at cycle start, thus at sync pulse falling edge.....
BUT
-Figure 63 on page 36 shows real case scoped signals. Polarity of signals here seem counterdicting explainations; Anyway CH1 here transition high a little while after the sync falling edge. So, if confirmed, a little inverting buffer may do.
Question:
1) what am i missing? Is it that CH1 is 0°, and CH2 & CH3 are 180° rotated, instead? This would explain everything.
2) Apart from the reasons, will CH1 always have it's rising edge within a reasonably little time from sync fall, for every TPS DUTY CYCLE?
Thanks, Francesco
