UC3875: The duty cycle is not 0.5

In the situation of no load, the duty cycle of outA\B is about 0.4\0.6.

From the scope, I can know that the delayset of A-B is normal. Also, The CS pin didn't exceed 2.5V.

I am using UC3875 on the peak-current-mode phase-shift full-bridge converter.

The CS pin is connected to GND with a 0ohm resistor. I am not using the current-limit fuction of UC3875.

And now the unstable situation didn't appear.

 Dear user6154919,

I am pleased hear from you. I think you have to take care 2 points.

1, since the min delay time of OUTA and OUTB is 150ns, you can't get absolutely 0.5 duty cycle. But, You can change the R_delayset to design different delay time.

2, if you found that delay time of OUTA and OUTB is 150ns already, please check the driver delay time and the driver push- source current whether is enough to drive your mosFET.  You can use driver which have greater current. and you can try to change driver Resistor value to lower. 

Dear,

Maybe I misunderstand your question last time.

Can you capture OUTA and OUTB waveform on the UC387 PIN and show here?

thanks

Hi,

Thanks for your reply.

The first two pictures are normal situation. The Ton and Toff are alomost equal. The dead time is 300ns. (CH1-OUTA, CH2-OUTB)

But the following two pictures are abnormal ones. The Ton of CH2 is 8.08us, the Toff of CH2 is 9.84us. The difference is too large. Also, the CH1's Ton>Toff. (CH1-OUTA, CH2-OUTB)

Best Regards,

Ben.

Would it be the noise that affected the nramal function of UC3875?

If so, how can I detect which pin was polluted and how to improve the situation?

Not only the duty cycle of outA\B can be mistaken, but also outC\D can also be mistaken. As the following picture shows, CH1-outC, CH2-outA, CH3-EAout, CH4-the primary current of the transfrmer.

Dear user,

since there is no timing diagram in the UC3875 datasheet, I copy from other phase shift controller as attachment for you reference. according to the timing diagram, I you can get the information what is the decision conditions of the OUTA/B ON or OFF. the key is the SYNC and Freq waveform. so, can you please double check the waveform on the PIN SYNC(17) and Preqset(16) compare with the OUTA/B. you can show the waveform here if you are available.

If you find there is noise on these PIN, you have to find the noise source and fix it.

let me know your status.

thanks

Hi,

I have captured the pin(fset) as the following picture. CH1-OUTA, CH2-OUTB, CH3-fset. The waveform did have some noise that affected the timing diagram.

The following picture is the sync pin---CH3. It did have noise on this pin. But I don't know if it affect the timing diagram. In some place, the voltage of SYNC exceed the high voltage but the OUT is still high. 

I don't know how to improve the chip anti-interference.

Dear user,

It seem that the signal of FREQ is disturbed.

It is difficult that fix the noise issue through theoretical analysis. So, you have to try  variety of way to solve this issue by yourself.

Here, I just give you some proposal according to my experience before. I hope it is useful to you.

1,You need to pay attention the function of ZVS is achieved. If there is hard switch situation, there is great current noise in the circuit loop. You can increase the delay time and increase the inductance of Lr to improve the performance of ZVS.

2, A good  PCB layout is basic. So, double check you PCB layout and find the doubts you think. double check whether the signal GND trace and the power GND trace are separated.

3,try VCC from outside aux DC supply.  

Hi,

Thanks for your reply.

I'll try as you advised.

Best Regards,

Ben.

Hi，

I have tried VCC from outside aux DC supply, but it didn't seem to be useful. The phenomenon still esists. OUT A  and OUT B almost remains to be 0.53/0.42 or 0.42/0.53.

Would you please reccommand some PCB layout of UC3875 application?

Thanks a lot.

Best Regards,

Ben.

Hi Ben,

I am sorry I have no PCB layout guideline on hand. you refer to the UCC28950 EVM layout: www.ti.com/.../sluu421a.pdf.

what is the condition when the Duty cycle abnormal ? light load  or  heavy load?

thanks

Hi，

Thanks for your reply.

In only control supply, the waveforms are correct.

Also, in openloop conditions, the driver waveforms are correct. And I tried 200W load, it's still OK.

However, in closed loop condition, when I tried 100W load, the driver waveforms became abnormal. Sometimes, OUTA(~0.53) > OUTB(~0.41); sometimes, OUTB(~0.53) > OUTA(~0.41). 

Thanks,

Ben.

Hi,

I wonder if a 1.3V dc offset added to the pin RAMP, would it be useful to improve the situation?

Since I can't figure out how to add this dc offset, do you have any ideas?

Thanks.

Best Regards,

Ben.

Hi Ben,

Yes, you can try it. You can put a push Resistor to 3.3v to get DC offset.

but, I am worry that it is not useful for this issue. because OUTA/OUTB  ON and OFF is determined by the Sync not the RAMP.

Thanks

Hi,

Thanks for your advice,

It doesn't work to get DC offset. I also think it is useless to solve the problem of OUTA/B.

I have no idea now:(

Best Regards.

HI Ben,

I think the most importance thing is what to find the noise and fixed it.

thanks

Hi Ben

Many problems like this are due to noise injection caused by the PCB layout so it would be really good if you would share your PCB Gerber files with us so that I can review them. Please also include your schematic files. If you don't want to post them to this public forum then please send them to me at 

colingillmor@ti.com

As Bliss said we don't have a specific layout recommendations for this device but there are some general purpose guidelines at https://training.ti.com/pcb-layout-smps-part-1-2?context=1134585-1139234-1136886  and https://training.ti.com/search-catalog?keywords=PCB+layout+for+smps&start%5Bdate%5D=&end%5Bdate%5D= which are useful.

Regards

Colin

Hi, Colin

Thanks for your reply.

I have sent the schematic files and PCB Gerber files to you on Nov. 21,

I will very appreciate it if you can see them and give me some suggestions.

Best Regards,

Ben.

Hello Ben

I've been able to open the layout files - my apologies, I had forgotten that you had sent them to me. I've sent you some comments by email. The main thing is that the ground connections at the IC need to be improved.

Regards
Colin

Hi,

Thanks for your reply. I have received your e-mail.

I will try as you advised.

Thanks.

Best Regards,

Ben.

Hi,

it is long time you have no reply. I am going close this thread now. if you have more question, you can create new thread to discuss.

thanks

Sorry.

I have tried everyway that you advised, but it doesn't seem to be useful.

Thanks.

Hi Ben,

Did you change you PCB layout according to Colin's proposal who had sent email to you before?

Layout Review.docx

thanks

Hello,

According to Colin;s advice, I have tried to remove the IC, place a layer of Polyimide (Kapton) or other high temperature tape over the area occupied by the IC. Then place a copper tape over the Kapton and connect it to pins 12 (PGND) and 20 (GND), add a second layer of tape as an insulator. Then replace the IC. 

However, the experiment result shows that the improvement does't seem to be useful to solve the problem of OUTA/B.

Now, I am wondering if there is a way that I only need to drill somewhere on the PCB to disconnect the power gnd with control gnd.

I will very appreciate it if you can offer me some advice.

Thanks,

Ben

Ben,

I am not sure that the issue can be resolved if you just want to rework on you original PCB rather than Do the new PCB.  Since you know that there are so much Parasitic parameters on your reworked PCB. It maybe make more noise on you PCB.

Could you please show the PCB picture after you reworked here?

thanks