TPS65218D0: ISR mechanism

Ranjith,

I am assigning this question to the Processor team. I support the TPS65218D0 device but am not sure how the ISR works in the SDK.

Hi Ranjith,

Which TI processor and SDK you are using?

Regards,
Pavel

Hi Pavel,

We are using NXPs processor and SDK version is 4.14.98.

Thanks,

Ranjith

Hi Pavel,

Thanks for your information. We will ask NXP support team regarding this query.

Regards,

Ranjith

Ranjith,

I apologize, I did not know the question was related to NXP processor. We can assist with your question related to the PMIC. Please allow me a couple days to discuss with the software team and then I will reply.

Hi Brian,

Thanks for your concern. We are using NXP processor but the question was related to TI PMIC only. Take your time to discuss with your software team and let me know the status.

Thanks,

Ranjith

Ranjith,

For the purpose of this discussion, I will refer to TPS6521815, the user-programmable version of the TPS65218xx device.

TPS65218D0 is EEPROM specifically programmed for Sitara AM335x & AM437x attach, while TPS6521825 is EEPROM programmed specifically to work with LP873347 to power the NXP i.MX 8M Mini/Nano.

In general, the interrupt service routine flow would be as follows:

1. Interrupt pin (nINT) of PMIC (TPS6521815) changes from high to low state, which toggles interruptible GPIO on NXP i.MX6/7/8 processor
2. Processor reads INT1 (0x01) and INT2 (0x02) registers of the PMIC (I2C slave address 0x24) to identify which interrupts were triggered
3. Processor records value of important interrupts and handles them appropriately
4. Processor writes back same value to INT1 (0x01) and INT2 (0x02) or 0x3F to both registers to clear all interrupts
5. Processor reads INT1 (0x01) and INT2 (0x02) registers again to confirm the data returned is 0x00 for both
6. For persistent interrupts, an error message may be necessary. Repeat Steps 2-5 when Step 1 occurs again

Important interrupts to handle and report via Terminal in Linux:

• HOT (INT1, bit 2) - error message should read: "Power supply early thermal shutdown warning. System will shutdown automatically"
  • If this interrupt occurs, the processor must transition to a low-power mode or the OFF state as soon as possible before the PMIC is forced to shutdown on its own
• LS3_F (INT2, bit 5), LS2_F (INT2, bit 4), and LS1_F (INT2, bit 3): "Load switch [x] exceeded operating temperature limit and will be disabled until next manual re-boot of system."
  • If this interrupt occurs, the PMIC shutdown a load switch automatically but this will not impact the rest of the power supplies. Therefor, no immediate action must be taken
    
• LS3_I (INT2, bit 2), LS2_I (INT2, bit 1), and LS1_I (INT2, bit 0): "Load switch [x] is actively limiting the output current (output load is exceeding current limit value). Load switch will be disabled if problem persists."

• On the second occurrence of this interrupt, it would be wise for the processor to manually disable the load switch and report "Load switch [x] is disabled due to persistent over-current condition"

It is likely that none of these interrupts will clear the first time they are read because the condition still exists. This is why some action must be taken (automatically or manually) to ensure the interrupt is eventually cleared.

The other interrupts are related to processes that are initiated by the processor (VPRG, PRGC, and CC_AQC) or platform specific (AC and PB), for example due to operating from battery-power vs. line power. These do not need to be handled by a generic Linux ISR because it is unlikely that action needs to be taken or that they will be generated at all.

Specifically, for NXP i.MX6/7/8 systems, we are not connecting the PB pin of the PMIC to a push-button because the processor itself has an ON/OFF input connected to a push-button which manages the On/Off state of the system.

Hi Brian,

Thanks for your detailed explanation on the working of ISR for TPS65218 PMIC. This information will be very helpful in our design.

Regards,

Ranjith