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TPS65950: incorrect arxl1_apga_ctl reg description

Brian Bennett1
Prodigy 40 points
Part Number: TPS65950

In the TPS65950 OMAP document ("TPS65950 OMAP(TM) Power Management and System Companion Device ES 1.2 TRM (Rev. G)" at  http://www.ti.com/product/TPS65950/technicaldocuments), the ARXL1_APGA_CTL Register (table 14-38 on page 758) definition shows 5 bits (7:3) for the ARXL1_GAIN_SET field, but the description only goes to 4 bits (0xF). Does anybody know the correct interpretation of the ARXL1_GAIN_SET field? (i.e. should I just ignore bit 7, or is bit 3 the one to be ignore? Or should it really be a scale of 1dB per number (i.e. 0x0 is 12dB, 0x1 is 11dB, 0x2 is 10db, ... 0x1F is -18dB) instead of 2dB(i.e. the current, incorrect description has it as 0x0 is 12dB, 0x1 is 10dB, 0x2 is 8dB, ... 0xF is -18dB)? 

  • 0
    TI__Genius 12735 points

    Hi Brian,

    I reviewed the TRM you referenced and it looks like you should only use up to 0xF based on the list in the register description. In this case you should be using bits 6:3 to write these values.

    Best regards,

    Layne J

  • 0 in reply to Layne J
    Prodigy 40 points

    Hi Layne,

    Would you agree that bit 7 would then be ignored (and writing either a 0 or 1 won't  affect anything)?

    thanks,

    Brian

  • 0 in reply to Brian Bennett1
    Prodigy 40 points

    Hi Layne,

    A colleague just realized that the ARXR1_APGA_CTL Register, as well as ARXL2_APGA_CTL and ARXR2_APGA_CTL (which are tables 14-39 through 14-41), continue on past 0xF, to 0x10, 0x11, and 0x12 (corresponding to -20dB, -22dB, and -24dB, respectively). I presume ARXL1 should follow this pattern, but can you confirm? (additionally, the documentation stops at 0x12 but has the dots that seem to imply it continues. Do these continue on to 0x1F, or do values higher than 0x12 just mean the same setting as 0x12?)

    thanks,

    Brian

  • 0 in reply to Brian Bennett1
    TI__Genius 12735 points

    Hi Brian,

    I would consider bit 7 of that register to be an unknown bit and I would read what the default value of bit 7 is and keep that consistent when you make changes to that register. I would recommend doing additional testing on these bits if you would like to see if -20dB, etc are a possible value for this register. 

    Best regards,

    Layne J