• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 62 subscribers
  • Views 141 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMR23625: External clock input requirement

Taketo Sato
Genius 9475 points
Part Number: LMR23625

Hello team,

I have questions about SYNC input. Could you please let me know below?

  1. Is there any requirement for T2 and T3?
  2. For T1, can I think its requirement is Tsync_min?
  3. Is it correct understanding that the device detects timing of external clock's low to high edge?
  4. How many external clock cycles is required for the device to start running with the external clock?
  5. Datasheet p.13 says "SYNC amplitude threshold of 2.8 V (typical)". How much variation on the threshold voltage should we consider? for example, like it should be within 2.8V+/-100mV. 

Best regards,

  • 0
    TI__Expert 4555 points

    Hello Taketo Sato,

    I am discussing your questions with the system and design internally. Please allow us a couple of days to answer your questions. Thanks for your patience. 

    Best Regards,

    Ankit Gupta

    Application Engineer

  • 0 in reply to Ankit Gupta95
    TI__Genius 9475 points

    Hello Ankit-san,

    Could you please support this?

    Best regards,

  • 0 in reply to Taketo Sato
    TI__Expert 4555 points

    Hello Taketo Sato,

    Answering your questions below:

    1. Is there any requirement for T2 and T3? - It is not spec'ed. The design has no specific requirements regarding T2 and T3.
    2. For T1, can I think its requirement is Tsync_min? - Typical minimum On and OFF time is 100ns (We don't have min and max for this spec) 
    3. Is it correct understanding that the device detects the timing of an external clock's low to the high edge? - Yes
    4. How many external clock cycles are required for the device to start running with the external clock? - There is PLL inside the design, and it cannot be spec'ed. It depends on the temperature and process corner on how much time PLL takes to get lock with an external clock. 
    5. Datasheet p.13 says "SYNC amplitude threshold of 2.8 V (typical)". How much variation on the threshold voltage should we consider? for example, like it should be within 2.8V+/-100mV. - The EC table says 2.8V(min) while the EN/SYNC description says 2.8V(typ.). We confirmed internally with designer and Product Engineer that 2.8V is actually "minimum spec" not typical.

    Let me know if you have more questions. 

    And please close the thread if you think my response answered your questions. Thanks!

    Best Regards,

    Ankit Gupta

    Application Engineer