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CCS/UCD3138A64: UCD3138A64

Part Number: UCD3138A64

Tool/software: Code Composer Studio

Hi every one, i am using UCD3138A64 to power conversion designer has designed when the input voltage between 12vdc to 75vdc output should be 12v dc how to do this could any one tell me solution please?

I have read datasheet i have understood through front end, filter and from dpwm we can set output, i have also downloaded code from ti website, i couldn't able to understand register setting of front end i attached below could any one expalin me the functiopn and register settings please.


void init_front_end0(void)
{
FeCtrl0Regs.RAMPCYCLE.bit.SWITCH_CYC_PER_STEP = 0;// every switching cycles pre DAC step
FeCtrl0Regs.RAMPCTRL.bit.RAMP_EN = 1; // Ramp by Hradware
FeCtrl0Regs.RAMPCTRL.bit.SYNC_FET_RAMP_START = 0; // default, start sync-FET at zero
FeCtrl0Regs.EADCDAC.bit.DAC_DITHER_EN = 0;// default, Disable dithering
FeCtrl0Regs.RAMPDACEND.bit.RAMP_DAC_VALUE = 12000; // 0.09765625 mV/Count
FeCtrl0Regs.EADCDAC.bit.DAC_VALUE = 0; // Start point for ramp-up
FeCtrl0Regs.DACSTEP.bit.DAC_STEP = 1024;// increment by 0.096mV per step. Getting ramp up time at 60ms

FeCtrl0Regs.RAMPCTRL.bit.RAMP_SAT_EN = 0;
FeCtrl0Regs.RAMPCYCLE.bit.DELAY_CYCLES = 0;


FeCtrl0Regs.EADCCTRL.bit.AFE_GAIN = 3;// Gain X8
FeCtrl0Regs.EADCCTRL.bit.EADC_MODE = 0;//?
FeCtrl0Regs.EADCCTRL.bit.SCFE_GAIN_FILTER_SEL = 1;//
FeCtrl0Regs.EADCCTRL.bit.SCFE_CLK_DIV_2 = 0 ;//?
FeCtrl0Regs.EADCCTRL.bit.SCFE_ENA = 1;//
FeCtrl0Regs.EADCCTRL.bit.EADC_ENA = 1;
}


void init_front_end1(void)
{
FeCtrl1Regs.RAMPCYCLE.bit.SWITCH_CYC_PER_STEP = 1;// Number of switching cycles pre DAC step
FeCtrl1Regs.RAMPCTRL.bit.RAMP_EN = 1; // Ramp by Hradware
FeCtrl1Regs.RAMPCTRL.bit.SYNC_FET_RAMP_START = 0; // default, start sync-FET at zero
FeCtrl1Regs.EADCDAC.bit.DAC_DITHER_EN = 0;// default, Disable dithering
FeCtrl1Regs.RAMPDACEND.bit.RAMP_DAC_VALUE = 2000; //output is 12V ;10240; // End point for ramp-up 1 Volts, 0.09765625 mV/Count
FeCtrl1Regs.EADCDAC.bit.DAC_VALUE = 4000; // Start point for ramp-up
FeCtrl1Regs.DACSTEP.bit.DAC_STEP = 100;// 640/200 = 3.2 // 11.00,1100,1100,1101 for 1mS ramp up
FeCtrl1Regs.RAMPCTRL.bit.RAMP_SAT_EN = 0;
FeCtrl1Regs.RAMPCYCLE.bit.DELAY_CYCLES = 0;


FeCtrl1Regs.EADCCTRL.bit.AFE_GAIN = 3;// Gain X8
FeCtrl1Regs.EADCCTRL.bit.EADC_MODE = 0;//?
FeCtrl1Regs.EADCCTRL.bit.SCFE_GAIN_FILTER_SEL = 1;//
FeCtrl1Regs.EADCCTRL.bit.SCFE_CLK_DIV_2 = 0 ;//?
FeCtrl1Regs.EADCCTRL.bit.SCFE_ENA = 1;//
FeCtrl1Regs.EADCCTRL.bit.EADC_ENA = 1;

}


////////////////////////////////////////////////////////////////
//
// Used for feed forward Vin sensing (EADC2(FE2))
/////////////////////////////////////////////////////////////////

void init_front_end2(void)

{

FeCtrl2Regs.EADCDAC.bit.DAC_DITHER_EN = 0;// Disable dithering
FeCtrl2Regs.EADCDAC.bit.DAC_VALUE = 7000; // (70/193.55)*1.6 Volts //4000 for primary side 20V
FeCtrl2Regs.EADCCTRL.bit.AFE_GAIN = 0;// Gain X1
FeCtrl2Regs.EADCCTRL.bit.EADC_MODE = 0;//
FeCtrl2Regs.EADCCTRL.bit.SCFE_GAIN_FILTER_SEL = 0;// For faster signal acquisition
FeCtrl2Regs.EADCCTRL.bit.SCFE_CLK_DIV_2 = 1 ; // For faster conversion
FeCtrl2Regs.EADCCTRL.bit.SCFE_ENA = 1;//
FeCtrl2Regs.EADCCTRL.bit.EADC_ENA = 1;
}

Thamking you.