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TPS546C20A: Minimizing the startup time

Per Magnusson
Intellectual 500 points
Part Number: TPS546C20A

I use TPS546C20A in a design and would like it to start ramping as soon as possible after the 12 V input is available. The datasheet does not seem to say much about how long time one should expect from available input voltage to the start of the ramp. The time I see is about 12 ms, which is longer than desired.

BP3 and BP6 have reached their final levels much less than 1 ms after the input has reached 12 V.

CNTL is unconnected (pulled high internally).

ON_OFF_CONFIG is 0x16 (wait for CNTL only)

TON_DELAY is 0x00 (0 ms delay)

VIN_ON is 0x12 (start at 4.5 V)

TON_RISE is 0x05 (5 ms rise time)

The register description for TON_DELAY talks about a "start condition"; but the meaning of this term is not defined as far as I can see. Does it involve more than available input voltage as defined by VIN_ON and the condition defined by ON_OFF_CONFIG (that CNTL is high in my case)?

I really would like the ramp to start within 1 ms of 12 V being available, rather than after 12 ms. Is the 12 ms delay something inherent in the TPS546, or is there something with my design that causes it to wait a bit before starting the ramp?

Here is a plot of the waveforms for 12 V input, BP6, BP3 and the output voltage:

Per

  • 0
    TI__Mastermind 48200 points

     

    The TPS546C20A has some internal delays between its AVIN power-up and when it can start responding to the CNTRL pin in order to detect the state of the VSEL and SS pins that will likely result in a 1ms delay being unobtainable, however 12ms seems excessively long.

    Can you re-take the start-up waveforms and include the CNTRL pin to see when the CNTRL pin rises above 1V to determine of the floating CNTRL pin is delaying the start-up?

    Additionally, can you use an oscilloscope probe on the VSEL and SS pins to monitor their detection attempts during start-up.  During start-up, the TPS546C20A will force a current out of the VSEL and SS pins to attempt to detect the resistance ground.  To protect the circuit from noise, multiple detection attempts are made until consecutive measurements produce the same results.  If there is excessive noise on the VSEL or SS pins, it would increase the number of attempts made, extending the power on to enable delay.

  • 0 in reply to Peter James Miller
    Intellectual 500 points

    Thanks Peter.

    I did the measurements you suggested and they look fine (CNTL reaches full amplitude even before 12 V does, and with 2 ms/div I just see a single small pulse on both VSEL and SS at the same time that CNTL reaches full amplitude).

    In the process I did however discover the real culprit. I want to synchronize the TPS546 to an external source which is not available until a while after the output of the TPS546 is stable. Before this, the SYNC input is low. I think this caused the regulator to be a bit hesitant to start, but when I set both SYNC_FAULT_DIS and FORCE_SYNC_IN to 1, the startup delay goes away and the ramp on the output starts within less than 1 ms of the input reaching 4.5 V. (Setting just FORCE_SYNC_IN to 1 while leaving SYNC_FAULT_DISABLE did not eliminate the 12 ms delay.)

    So this is now resolved.

    Regards

    Per

  • 0 in reply to Per Magnusson
    TI__Mastermind 48200 points

     

    Yes.  Whent he TPS546C20A is programmed for SYNC IN, the TPS546C20A will delay its start-up until an external SYNC signal is available.  By programming the TPS546C20A to Force SYNC IN and to disable the SYNC FAULT, it will start-up in SYNC IN mode without an external SYNC and then convert to the external SYNC once it detects the external SYNC on the input.

    I am glad that we have this issue resolved.  If you have any other questions or issues with the TPS546C20A, please start a new E2E thread.