UC1825: ESD clamp

Hi Carlo,

I will have to ask the IC design team in the US for some help on this, what is the amplitude of the line voltage that the customer is referring to ?

Can they share the schematic or partial schematic that shows the ramp pin connections?

Thanks

Peter

Hello,

The application is essentially the same as shown in the attached illustration from the UC1825 datasheet.  The line voltage (Vin) is 18V-40V_DC.  The UC1825 oscillator output is used to drive the ramp reset transistor.  I'm concerned that if the UC1825 power source is shutdown or temporarily disconnected, that the ramp pin might be pulled up to the primary input bus voltage.  This would theoretically not be a problem if there is some ESD or other clamp internal to the UC1825 on the ramp pin.

Regards,

Steve

 Ramp.docx

Hi Steve,

Thanks, I have a call with IC design team on Monday of next week and I will get this request added to there list. It may take a few days for them to respond after that.

Regards

Peter

Hi Steve,

Sorry for the long delay here, this task is still with the IC design team and I have reminded them of this again today.

I hope to have an update by the end of the week.

Regards

Peter

Hi Peter,

Thank you for taking time to respond to this issue.  Does this also apply to the UC1823 and UC1824, which we also use?  Can you tell me the nominal zener clamp voltage for the 1A ESD device?  Would like to know the value to assess the nominal stress on the ramp capacitor and ramp reset transistor.

Regards,

Steve

Hi Steve,

Let me check.

Regards

Peter

Hi Steve

Sorry for the delay here I am chasing the IC team for a response on this.

Thanks

Peter

Hi Steve,

The internal ESD protection device is not intended to be use as a clamping structure external to the part. 

In terms of voltage stress during normal circuit operation the best guidance we can give is that the voltage on the RAMP pin is to not exceed the abs max stated in the datasheet.

Regards

Peter