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TPSM82480: TPSM82480 Instable or don't reach the Vout setting

Part Number: TPSM82480


I've a board with 3x TPSM82480 devices.

One to generate 1.2V (from 3.3), another to generate 1.0V (from 3.3) and the last one to generate 1.8V (always from 3.3).

The first two are working fine, but we have issues with the one for the genearation of the 1.8V.

If I use the "standard" values for the resistor divider (R1 =240K, R2= 120K) as proposed by the web tool, the device is clearly unstable (even with the Feedformwrd capacitor of 36pF.

I've tried to lower the values of the resistor, keeping the same ratio, in order to increase the current flowing into the resistor divider. Now R1=150K and R2 is 75K.

The Vout become stable but it not reach the target value of 1.8V ... it is stuck at 1.2V and no way to change it ....

Any suggestion, please ?

Thanks in advance and have a good day.

  • H Andrea,

    Can you share your schematic and PCB layout?  How much additional output capacitance is present on the output, including at the load?

    Does this behavior occur on more than 1 PCB?  Can you share a waveform of Vin, Vout, FB, and PG?

  • Hi Andrea,

    Were you able to solve this or do you still need to debug it?

  • Hi Chris,

    Sorry for the late.

    As far as the PCB layout, this has been done using the layout example provided by the datasheet....  Same layout than the previous devices ...

    And yes, same behaviour on others PCB that i've recently received ...

    The main difference from the other two devices is the amount of load capacitors.

    The devices that working fine they actually see something like 100uF or so ....

    The device that doesn't work is used to provide the 1.8V of Vccaux of Xilinx FPGA and provide the for differents lower voltages stepdown converters (TPS7A8xxx family), so, well, it can actually have a lot of load capacitors.

    First estimation is around 600uF or greater ....

    I'm quite sure that it is a stability/protection problem on the TPSM82480 and not something about the load (everything is fine when i remove the TPSM and put an external power supply,).

    I've found a couple of lines in the datasheets that tell me that, if "large" amount of load capacitors is used, it is necessary to have capacitor on SS pin to avoid foldback peak current limits ...

    Today i've a 10nF capacitor on SS pin .... it is enough ?   Is this the reason of the instability ?

    I've tried also to use the PSPICE transient model you provide to simulate it in my TINA, but i've not success to convert it in a schematic macro ...   Some clues ?

    Thanks in advance



  • Hi Andrea,

    Thank you for explaining.

    600uF is way too much.  This is explained in section of the D/S.  Is the 600uF electrically connected to the 1.8V output or is it after the LDOs?  Can it be reduced?  

    A waveform of Vin, Vout, SS/TR, and EN would help me understand what you are seeing.  But it is most likely related to the excessive output capacitance.

  • Hi Chris,

    Yes, I have a lot of decoupling capacitors (several hundreds of uF) connected directly to the 1.8V .... before the LDOs  ...

    I've understood that the 4x47uF are just necessary for the stability and that i can add more to stabilize the loads and filter the rejections of the other bucks/LDOs...  am I wrong ?

    What can I really consider to add as load capacitors to maintain the TPSM stable ?

    Tomorrow morning i will try to reduce the load caps and provide to you a screenshot of the scope, but i'd like to know where are the limits to not pass....



  • Hi Andrea,

    Unfortunately, the device cannot distinguish between how much capacitance is present for its stability and what is present to decouple the loads--all this capacitance is electrically connected to the same net--the module's output voltage.  This means that it all must be considered and will affect stability.  The D/S recommends using less than 150 uF effective capacitance.  This assumes ceramic caps with no ESR.  This amount of capacitance should be safe and allow the device to be stable.

    You may be able to support a bit more in your application, and this can be determined through a bode plot of the power module.  It is best to run a bode plot on a stable system (with some caps removed) and then see how much phase margin you have.  This is the usual measure of stability for a power supply.

    Does the FPGA require this much capacitance?  These high values are usually no longer needed with modern power supplies, which have faster control loops.

  • Hi Chris,

    Some funny things happen today ...

    First one: on the 1.8V i've removed quite all load capacitors, results: the same ...  it doesn't work

    Second: on the same board with depopulated capacitors,  i've take the TPSM that provide the 1.2V ... re-tuned to bring out 1.8 and connected it to the 1.8V load .....  It works !

    Third: i've received some new PCBs ...  that's mean full load capcitors ... and .... the TPSM that provide the 1.8V works !!

    I'm happy that it works, but now i'm not sure to understand ...

    Ok, probably on the first two boards there has been an assembly issue (looking more closely the device seems a little bit "shifted" on the PCB landing pads), but how can we explain the fact that, at full load capacitors, the TPSM82480 works  and is stable ?

    Thanks in advance


  • Hi Andrea,

    Thank you for sharing your testing results.  Did you just test 2 boards initially?  That's a very small sample size and it's likely the same manufacturing/soldering issue affected both of them.

    The 150 uF limit assumes all ceramic capacitance.  Is your 600 uF all ceramics?  Can you send the actual part numbers for those caps which are over 5 uF?

    Are you able to run a bode plot on these circuits?

  • Hi Andrea,

    Did you get a chance to measure some waveforms or bode plots?  What type of output caps are you using?