UCD9081: UCD9081

Sorry but I need a formal answer,

and I have more question:

3. Is the only way to pause the start of the sequence is to hold the reset leg?

4. When there is an error, is it possible to receive an alert from one of the GPOs?

if no, how dose the UCD9081 inform error?

5. If after activating the component I lower the rest to 0, does the component perform power sequence down for all the output?

HI

There are many ways to shutdown the powers. such as toggling REST pin of UCD9081, issue commands, or use a monitor pin to monitor a external signal to trigger a UV fault to shutdown. Application shall pick up one which is best to fit its own case.

When the device is out of reset, it will start the sequencing based on the setting. holding reset low is the way to delay the re-sequencing.

UCD9081 offers 4 GPO output. these output can be controlled by any rails. so when rails have a fault, the GPO can be shutdown by the  rail's fault. this may be a way to notify the host. you can read the UCD9081 document at www.ti.com to understand these  features. Or you can poll the device status to see whether there is a fault or not.

when UCD9081 is forced to reset by external reset signal. All IOs are back to Hi-Z default state immediately. This shall disable the power. but there would be no power down sequencing based on the configuration.

Regards

Yihe.

thanks, one more question, 

what is the during time between the UCD9081 read the address resistors from the GPOs and the UCD9081 give GPO first output value?  

HI

It takes about 35ms time for UCD9081 to give GPO first output value.

Regards

Yihe

Another question for the reset pin I see the note:

"

9.2.1 Design Requirements

RST pin must have a 10-kΩ pullup resistor to 3.3 V and 10-nF decoupling capacitor to ground. The component
must be placed as close to the RST pin as possible

"

If I want to connect pull down to the reset pin and enable the reset pin from my CPLD instead of the 10K and 10nF termination, it is ok?

or I must do the 10K and 10nF termination and buffer it to to the CPLD (with FET)?