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Detailed description of "shutdown mode"?

David Good
Prodigy 30 points


Several of the linear regulators I've read about have an EN (enable) pin which can be used to disable the device and enter "shutdown mode."  These devices boast extremely low quiescent current in "shutdown mode," however I am unable to find any other information regarding the functionality of the device in this mode (there's no further information in the datasheet...).

What exactly does "shutdown mode" entail?

Thanks.

David Good

  • 0
    TI__Mastermind 36110 points

    The shutdown terminology is intended to explain that the IC is turned off.  All internal circuitry is turned off and there is no output voltage.  When the LDOs are enabled, their current consumption rises because it takes current to power their internal circuitry.  You will find the quiescent current specifications in the datasheet.  These are different from shutdown current.

  • 0 in reply to Matthew Day
    Prodigy 200 points

    When you say the IC is turned off, you mean the inputs and outputs go to a HiZ state? In that state, is there any isolation between the IC pins and the external environment? And between the input and the output?

    What happens if I connect another power source in the LDO output when it's in the disabled state (i.e., if I have two power sources connected together)?

  • 0 in reply to Breno Rocha
    TI__Expert 8890 points

    Hi Breno,

    Unfortunately there is no industry understanding for what "Off" means. And in fact due to the physics of the mosfet there is no way to prevent backward, or reverse, current through the body diode of the main pass FET in the case where there is an output voltage higher than the input voltage - even during shut down.  During shutdown you can consider the Vin pin to be Hi-Z, and the FB pin is Hi-Z by definition.  But again the Vout pin is problematic and voltage on this can possibly cause uncharacterized current flow.

    Regards

    Bill

  • 0 in reply to Bill Stokes
    Prodigy 200 points

    Hello, Bill, thanks for the reply!!

    Considering what you said, I'll probably have problems with the design I'm considering now, with two power sources for the same power line (as in the image below):

    The buck converter would be constantly powered by the external power supply. When that external supply goes OFF, the LDO is turnned ON.

    The diode in the output of the buck converter is meant to eliminate problems with the LDO power going into the buck IC, but for the LDO I can't use that, as I need a low drop out (considering my battery voltage and my system voltage). Do you suggest something so that I don't have current flowing inside the LDO when it's disabled?

    Best regards,

    Breno Rocha.

  • 0 in reply to Breno Rocha
    TI__Expert 8890 points

    Brena,

    We run into this alot. Using an additional diode at the LDO increases loss and or forces you to run the mcu at a lower voltage. But unfortunately it is the best I can suggest.