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TLC59581: Problem with FC1 and FC2 access

Part Number: TLC59581

Hi,

I have two TLC59581 chips in daisy chain configuration. Clock and data signals are formed with FPGA. SCLK frequency is 2MHz, GCLK is 4MHz, data on SIN line is set up 150ns before SCLK rising front.

I can shift GS data into memory banks of both TLC59581 chips correctly. The following sequence is used:

  • shift 48 bits of GS data for the second chip in chain, along with 48 SCLK pulses
  • shift another 48 bits of GS data for the first chip, along with another 48 SCLK pulses
  • assert LAT and issue 1 SCLK pulse, then deassert LAT - this makes WRTGS command
  • repeat above steps 15 times, to fill one row of memory bank
  • repeat N times to fill more memory bank rows
  • assert LAT and issue 3 SCLK pulses, then deassert LAT - this makes VSYNC command

GCLK is being continuously provided. After the VSYNC command, both TLC59581 drive their LEDs in accordance with GS data pattern sent, which makes me think the 48-bit Common Shift Register inside TLC59581 chips is being accessed properly.

However, I cannot seem to write to FC1 and FC2 registers. The procedure used is almost similar to GS data pattern transmission:

  • assert LAT and issue 15 SCLK pulses, then deassert LAT - this makes FCWRTEN command
  • shift 48 bits of FC data, with first four bits being '1001' for FC1 or '0110' for FC2, along with 48 SCLK pulses
  • assert LAT and issue 5 SCLK pulses, then deassert LAT - this makes WRTFC command

EDIT. I am attaching capture of FCWRTEN followed by WRTFC1 with all zeroes.

At the moment there is no possibility to read FC1 and FC2 contents back, so I am using FC1 and FC2 values that would change the brightness and scan pattern on LEDs. For example, the FC1 value sent is all zeroes apart from '1001' bits 47-44, which I would expect to bring BC and CCR, CCG, CCB down to zero, effectively blanking the display. This however does not happen.

I am also slightly confused with number of bits for FC2 register said to be 44 (43..0), see Table 7. FC2 Register Bit Assignment in SLVA744 datasheet dated January 2016. This does not alight with Figure 6. Common Shift Register and Data Latch Configuration, which mentions 17 bits latched into FC2 from Common Shift Register, and Table 3. WRTFC/FCWRTEN Commands Description, which also mentions 17 bits:

"If ‘0110b’ is received for bit 47–44 of the common shift register, then the lower 17 bits in the common shift register are copied to the FC2 register"

Looking forward for any comments and suggestions.

Regards,
Tim