• State TI Thinks Resolved
  • Locked Locked
  • Replies 6 replies
  • Answers 2 answers
  • Subscribers 64 subscribers
  • Views 466 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TPS548A20: TPS548A20 bode plot measure

TPS548A20: TPS548A20 design question

user5968756
Prodigy 200 points
Part Number: TPS548A20


Hi Admin,

i want to have a 1V/15A, 3.3V/15A design. I check the webench and EVM's schematic and find some difference between. Could you pls help to answer it? Thanks.

1. Cin, Webench have 2.2nF Cin, but  EVM have 0.1uFCin. Which one are you perfer?

2. VREG, VDD, Cap is 2.2uF, EVM have 2pcs 1uF, Can i only use 1pc 1uF?

3. How much current the VDD would take? Can I use the 0402 0.063W resistor for VDD?

4. The EVM have bulk caps both for Cin and Cout, but Webench all have ceramic caps. Which one are you perfer?

Thanks,

YC

  • 0
    Prodigy 200 points

    Can i use 25V for Cboot?

  • 0 in reply to user5968756
    TI__Genius 14455 points

    Hi,

      Regarding 25V for Cboot, depends on your Vinmax. If it is typically less than 12V, you might be ok with a 25V Cboot. What is your Vinmax?

    For #1 Regarding the 2.2nF Cin cap, I am ok to use a 100nF cap as specified in the EVM. The purpose of this cap is to provide high frequency decoupling.

    For #2 For VREG, VDD, I would prefer to use 2.2uF - to ensure that you have enough capacitance.

    For #3, is the 0402 resistor to provide filtering to VDD?

    For #4, as long as you have enough ceramic capacitance to handle the load transients/ripple on the output and to handle the ripple on the input, you should be good. You can run load and line transients in WEBENCH siulations to get an estimate of the expected over/under shoot and verify if that would meet your design requirement.

    regards,

    Gerold

  • 0
    TI__Guru 56985 points

    YC,

    1. Cin, Webench have 2.2nF Cin, but  EVM have 0.1uFCin. Which one are you perfer?

    A high-frequency Cin bypass capacitor of 2.2-10nF will generally provide better high-frequency decoupling than a 100nF (0.1uF) bypass capacitor and would be preferred to limit the ringing on the SW node.

    2. VREG, VDD, Cap is 2.2uF, EVM have 2pcs 1uF, Can i only use 1pc 1uF?

    Either 1x 2.2uF or 2x 1.0uF would be preferred over 1x 1.0uF.

    3. How much current the VDD would take? Can I use the 0402 0.063W resistor for VDD?

    VDD will draw the gate drive and IC bias current, which will vary with switching frequency.  Unfortunately, the RF resistor is not included, so I can't see what the switching frequency is.  However, the current will be less than 30mA for switching frequencies less than 1MHz.  At 30mA, a 10-ohm resistor will dissipate 9mW of power, so a 0402 should be easily capable of handling the power dissipation.

    4. The EVM have bulk caps both for Cin and Cout, but Webench all have ceramic caps. Which one are you perfer?

    The TPS548A20 does not require bulk / electrolytic capacitors.  They are included on the EVM to help the evaluation board compensate for the long lead wires commonly used when testing boards in a lab bench environment.  Whether a customer design includes electrolytic (bulk) capacitors on the input or output is entirely up to the customer.

    5) Can I use 25V for Cboot?

    Cboot sees the voltage from BOOT to SW, which is limited to the Vreg voltage of 4.55 to 5.45V.  To minimize DC bias loss of capacitance, I would recommend using a minimum of a 16V voltage rating.

  • 0 in reply to Peter James Miller
    Prodigy 200 points

    Hi Peter,

    Thanks for your detai reply!

    What about other parameter?

    1. like the inductor value, Fs, Cout, Cin, Can I treat the webench's design as a start point? Can i directly copy webench's design? Then stuff some extra caps for the Cin and Cout.

    2. As we don't have the simulation tool to evaluate the bode plot, can i use the datasheet's Table 2 as a criterion? Do you think it's worth to do the loop gain measurement if the transient test and vripple are all looks good?

    Thanks,

    YC

  • 0 in reply to user5968756
    TI__Mastermind 25180 points

    1.  like the inductor value, Fs, Cout, Cin, Can I treat the webench's design as a start point? Can i directly copy webench's design? Then stuff some extra caps for the Cin and Cout.

    The webench and table 2 in datasheet are good starting points.    Many developers use the evm link to check the performance of their design.

    2. As we don't have the simulation tool to evaluate the bode plot, can i use the datasheet's Table 2 as a criterion? Do you think it's worth to do the loop gain measurement if the transient test and vripple are all looks good?

    There is no substitute for bench measurements.    A simulation can give insight on how specs change with variation in component values.

    If you are a pspice user, there is a model available for the TPS548A20