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CSD15380F3: Use as level shifter?

Benjamin Uhing
Expert 4295 points
Part Number: CSD15380F3
Other Parts Discussed in Thread: CSD13380F3

I have a new design I'm debugging that uses the csd15380f3 in two different places, one of which works and one of which doesn't. Can you take a look at my two applications and see if I'm doing something wrong?

Working:

I've got an FPGA with a Config_Done open drain output and an open drain StatusZ output that are both pulled up to 1.8V. When either one or the other of these signals is high-z from the FPGA and pulled up to 1.8V, the LEDs turn on as expected. The forward voltage of the LEDs is 2 V.

Not working:

This circuit is supposed to allow an external controller to send a power-bad signal (FMT_PG_VCCIO), which I currently have floating. I'm supplying VCCIO separately and have tried from 0V - 5V, but no matter the input to the gate of the FET, it won't start conducting. The source always measures at 0 V.

Am I using the FET in some way that isn't supported? I've triple-checked all the footprints on my board and they are right. I have 5 boards showing the exact same symptoms - U54-56 work, U51 doesn't, so I don't think it's an assembly problem.

Thanks in advance!

  • 0 in reply to Benjamin Uhing
    TI__Mastermind 36510 points

    Hi Ben,

    Thanks for the inquiry. For the working application, I would caution you that the minimum VGS where rds(on) is specified is 2.5V. You're pulling the gate up to 1.8V which is < 2.5V. If you look at Figure 7 in the datasheet, you can see that this is in the steep part of the curve where rds(on) increases exponentially as VGS decreases. Luckily, you're not driving any significant current so you're probably not seeing any problems in this application. However, small changes in threshold voltage due to process variations may cause problems turning on the FET. We have an alternative, CSD13380F3, in the same package and pinout that has rds(on) specified at VGS = 1.8V, in case you have any problems.

    For the non-working application, this is a high side switch and you need to make sure that the gate is pulled up higher than the voltage you're switching at the drain. When the FET turns on, source voltage = drain voltage (minus a small drop across rds(on)) and VGS = Vgate - Vdrain. In your application, VGS = VCC_IO - P1V8_LDO. Again, you need to insure VGS > 2.5V to guarantee rds(on). Also keep in mind that this FET has an ESD protection diode between gate and source. If the source voltage > gate voltage by more than a junction drop, it will forward bias the ESD diode and clamp VGS at a negative junction drop.

    I would suggest measuring VGS when the FET is supposed to be ON. How much current are you pulling thru the FET when it's ON? The max rds(on) at VGS = 2.5V is 4 ohms. You'd need about 450mA to drop 1.8V across 4 ohms. I am going to close this e2e thread. Feel free to email me at my TI.com email address if you have additional questions.