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TPS61220 sinking current through L pin during start-up when output voltage is present

Other Parts Discussed in Thread: TPS61220, TPS61220EVM-319

Hello,

I've been doing some testing recently with the TPS61220 converter and I've noticed an interesting issue that isn't specifically mentioned in the component's datasheet.  I apologize, this post will get a little long due to extra background information. Questions are in bold for convenience.  The converter was designed to output 5.5V.  My testing included three different operating scenarios that the converter would see in my application:

1) Functionality of the device when VIN and EN are tied together when no voltage is applied to the VOUT pin (the output of the TPS61220 is connected to a storage reservoir that may have a voltage as high as 5.5V). 

      - The result of this test was what would be typically expected with the TPS61220.  The converter began operating when VIN was between 0.6V and 0.7V and worked perfectly, outputting 5.5V to my storage reservoir and load.

2) Functionality of the device when the EN line is grounded and VOUT doesn’t have an externally applied voltage. 

     - This resulted in the converter not switching, which was expected since the EN line is grounded, and the input voltage passed through to VOUT through the internal pass through diode of the TPS61220.

3) And then my final operating scenario, functionality of the converter when the EN line is grounded and VOUT DOES have an externally applied voltage of at least 5 V from storage reservoir.

     - This result is where my question lies.  As VIN was slowly increased from 0V to the converter's start-up voltage, the L pin of the TPS61220 IC began to sink a large amount of current, as much as 200 mA.  This occurred when VIN was between 0.4V and 0.5V.  The output voltage of the converter was not changing, and no current was passing from the VOUT pin to the storage, so I don't believe any switching was occurring yet.  However, the sinking of current at startup is definitely not desired.

Here is my guess as to what is happening:  Based on the functional block diagram in the datasheet, it appears as if the Gate Driver is allowing the gate voltage of the low side drive NMOS FET to float, which is allowing the current to sink into the L pin, through the LSD NMOS FET, to ground.  Does that seem like a possible explanation?   Link to datasheet:  http://focus.ti.com/lit/ds/symlink/tps61220.pdf   See page 4 for the block diagram.

This sinking of current occurs until VIN exceeds ~0.5V, and then the converter begins to operate as expected once VIN exceeds 0.6V, outputting 5.5V as desired.  I've read through the datasheet for the TPS61220 trying to get an answer to why this occurs but I haven't found much of anything.  Another interesting tidbit, this hardly ever occurs when using a brand new TPS61220 IC, but almost always does after using the converter a handful of times.  Could this be related to a burn-in issue?  There has been one occurrence where this does happen with a brand new IC, but not typically.  I’m not violating any of the recommended maximum ratings with the converter circuit, so I don’t think its anything in particular that I’m doing that is damaging the IC, but I suppose I could be wrong.

Ultimately, is this result something that should be expected when an external voltage is applied to the VOUT pin of the IC and the converter has yet to begin its normal operation?  The component’s datasheet doesn’t mention anything specific towards the issue, such as using a series isolation diode between the converter’s output pin and the storage reservoir, but perhaps it's use is inherently implied?  

Sorry for the lengthy post.  I appreciate any thoughts you might have on the issue.

Scott

  • Hello,

    Thanks for your specific description.

    When Vout has an externally applied voltage, it can be looked as prebias voltage during startup. I have tested it based on the TPS61220EVM-319, change R2 to 100kohm to set Vout=5.5V, during different prebias voltage, such as 3V, 5.2V, 5.4V and 5.5V, it can work correctly.

    For the sink current into pin L, when the input voltage ramp up to the start point, the device will start to work, the output voltage is set to 5.5V which is higher than prebias voltage(3V, 5.2V, 5.4V), so the Mosfet switch to charge the output cap to 5.5V, there will be current sink into pin L, TPS61220 has a current limit, so the inrush current will be limited. If prebias current is 5.5V or above, there is no large sink current into pin L.

    The tested waveforms are as 4540.Test Waveform.ppt, for your information.

    For you application, you can test the pin L and output voltage during startup to check if the device work and the current charged into output cap.

    Thanks.

     

  • Thank you for your help with this.  I have a couple questions related to the test waveforms presented in the PPT file:

    -  What does PH stand for?  I would assume PMOS high side drive, but this would be a little confusing considering the synchronous rectifier FETs in the block diagram for the TPS61220 are NMOS (at least the arrows point toward the body for both FETs...implying NMOS)?   Or is there possibly an error in the block diagram?  Should the high side drive FET actually be a PMOS?

    - Also, it appears as if the EN was floating in the schematic...or was it actually tied low on the eval board but just not marked on the schematic?  Just a note...it was tied low in my application when my current sinking issue occurred during startup.

    Thanks,

    Scott

  • PH is short for the phase node, which is the switching node of the IC.  For the TPS61220, this node is pin L.

    Yes, EN was tied to the proper polarity to duplicate your conditions.  The figure was simply a copy and paste from the available documentation.