This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS549B22: Enable Pin Logic

Part Number: TPS549B22

Hi,

I am aware that pin 4 (EN_UVLO) can be used to set an under-voltage lockout voltage based on the voltage applied to the pin while PVIN and VDD are connected together. I am wondering if this IC has a master enable pin that shuts off the IC when tied high or low? 

  •  

    The TPS549B22 does not have a dedicated Disable function that fully disables the IC.

    With VDD = 12V and EN_UVLO = 0V, the VDD pin will draw approximately 700uA of bias current.  To reduce that further, VDD would need to be reduced below its UVLO level.  This can be accomplished by placing a P-channel FET between the VDD source and the VDD pin, but restarting the part from a VDD UVLO shut-down will require rerunning the pin-detection.