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CSD95472Q5MC: CSD95472Q5MC /PS parameters consideration / Vsw to Pgnd / Package

MINKYUNG KIM
Expert 1250 points
Part Number: CSD95472Q5MC
Other Parts Discussed in Thread: CSD95490Q5MC

Hello team,

I'm going to promote CSD95472Q5MC 60A and CSD95490Q5MC 75A.

1. Customer's requirement is 12V to 0.85V down for Virtex FPGA, using 7 phase buck controller with AVSBus. They are already using 60Amax power stage of competitior's, I chose these parts that have >60Amax. Is there any other parameter that I need to consider?

2. What's the meaning of these two parameters? I do not understand why it's classified into DC and 10ns pulse.

3. I see that CSD95472Q5MC's package is High-Density SON 5 × 6 mm. Then what is Q5MC? I also encountered RWJ, RWX, QVM several times. Are these meaning the die arrangements for better thermal dissipation?

Thank you for your prompt response!

  • 0
    TI__Mastermind 18200 points

    Minkyung, 

    Thanks for posting. See my answers below. 

    1) What you really need to consider is power loss. We can't know your thermal environment so we can't know the amount of power you capable of dissipating through a 5x6 QFN. If you know your specific RthJA of the power stages, and the max Ta they will be operating, you can calculate how much power each power stage can afford to dissipate, and you can select the correct power stages accordingly. 

    It is important that you use real system power loss as opposed to datasheet current ratings in selecting your power stage as there is no standard for current ratings for vendors to rate power stages. Some are more aggressive, some are more conservative. 

    2) We are providing a DC limit and and AC limit. The DC limit requires that the drain to source voltage of the FETs not exceed 20V. However, there is also an AC limit that implies that so long as it is a non repetitive event, the FET can absorb some avalanche energy when its breakdown voltage is exceeded. Exceeding the DC limit will not result in immediate failure but repetitive events can impact the long term reliability of the device. 

    Your system must be designed such that the 20V VSW limit is controlled below 20V. 

    3) The "Q5MC" is just a package suffix to designate this specific 5x6 QFN footprint. There are several 5x6 QFNs we have and each footprint will be unique. 

    For your knowledge, Q5MC and QVM (4x5) indicate proprietary TI footprints that are thermally superior to the common footprint package. RWJ is one of the industry common footprint 5x6 QFN packages and RWX is on of the industry common footprint 4x5 QFN packages. 

  • 0 in reply to Brett Barr1
    Expert 1250 points

    Brett,

    Thank you so much for your kind reply!

    Regarding your answer 1), Can you let me know CSD95490's RthJA? I can see RthJA of CSD95472Q5MC, 5 C/W max in DS but CSD95490's DS doesn't indicate this parameter.

  • 0 in reply to MINKYUNG KIM
    TI__Mastermind 18200 points

    I assume you are asking about the junction to top thermal impedance. 

    The junction to top thermal impedance of the CSD95490Q5MC is 5.8degC/W. It is still a thermally enhanced package with a thinned profile that puts the top high side die close to to the top of the package for minimum thermal impedance through the top. 

  • 0 in reply to Brett Barr1
    Expert 1250 points

    Apologize for the confusion, Yes I meant the junction to top thermal resistance. 

    Thank you so much for your reply!