Gentlemen,
I'm working on a three level Neutral point clamp (NPC) inverter for a motor drive and using the ISO5452 driver chip. The inverter is comprised of SiC mosfets/diodes.
I seem to be getting an erroneous DSAT trip when I reach a certain output current level. The DSAT trip occurs when Q1( the top transistor in a phase leg) turns off. The DSAT sense voltage begins to rise as it takes time for the DSAT diodes (connected to the drain of the mosfet) to block the voltage (Trr is rated at 75ns). The voltage does spike quite high during this time (20-25V) and apparently trips the chip off. Seems to be a function of the load current. Maybe since this voltage exceeds the Vdd voltage (19) this is also causing a problem?
I've tried to clamp this voltage with a 12V zener as shown in the app note ISO5452tiduc70a. That did not work. Maybe the zener is too slow.
I've also tried tying the RST pin to IN+ for an auto reset that would keep the chip in reset during the off time as suggested by the note in the data sheet 10.2.2.6 Auto reset on page 30(by the way, the schematic does not match what the words say and I did not follow what the schematic shows). But that doesn't seem to keep it from tripping.
Any suggestions or comments?
Thanks.
Richard Cummaro
Microchip Inc
(949) 280 5076