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TPSM53603: Design In Questions

d_zero
Genius 4430 points
Part Number: TPSM53603
Other Parts Discussed in Thread: TPSM53602,

Dear *,

few questions regarding TPSM53602, Vin=12V to 24V, Vout=5V, Iout,eff ~ 1.5A

1) Decoupling capacitor for V5V pin13

- there is no info in DS

- in EVM there is a un-populated  footprint

- in WEBENCH there is a 1uF capacitor

1a) is it recommended to use this capacitor on V5V pin?

1b) what is the recommended value?

1c) needs this pin to referenced to AGND or PGND?

2) Regarding feedback resistor

- there is recommended 10kOhm upper resistor

2a) can we change this resistor to 4k99?

2b) what is the drawback if this resistor is grater or lower value than 10kOhm?

3) There a recommended minimum Cin ( 2x 10uF) and Cout ( Table1)

3a) is there a max limit on Cin and Cout?

3b) in DS " When adding additional capacitance above COUT(min), the capacitance can be ceramic type, low-ESR polymer type, or a combination of the two."

can the output be also combination of ceramic + low-ESR tantalum capacitor like TPSD157K010R0050 ( 10V 150uF 10% 2917 ESR= 50 mOhm)?

3c) what is the max ERS allowed? also if we put 2 TPSD157K010R0050  in parallel then the effective ESR is lower and this is better?

https://e2e.ti.com/blogs_/b/powerhouse/archive/2019/09/17/options-for-reducing-the-mlcc-count-for-dc-dc-switching-regulators

3d) at what frequency should we observe the ESR ? because in most DS specification is @ 100khz.

4) can you provide the equation for calculating UVLO?

Best Regards.

  • 0
    TI__Mastermind 47060 points

    Hi,

    I've provided comments to your questions below:

    1a. The functional block diagram shows there is an internal decoupling capacitor internal to the part. Having an extra decoupling capacitor can be beneficial for V5V but is not required.

    1b. You can use the same 1uF capacitor detailed in the WEBENCH design if you want to include it in your schematic.

    1c. Reference it to AGND since it is the lesser noisy ground plane. 

    2a. Yes you can pick any resistor combination value you want. 

    2b. The drawback of using a lower resistor value is that it will pull more current. The large the resistor the more likely it will be affected by noise. The lower the resistor the more output current it draws.

    3a. You can see Section 6.3 for the limits of Cin and Cout.

    3b. Yes this should be fine. Usually the datasheet will require a minimum ceramic output capacitor to help reduce output voltage ripple. Any output capacitance after that can be full ceramic or a combination of ceramic and polarized capacitor.

    3c. There is no maximum ESR, the lower the better is my recommendation. Actually if you put a ceramic capacitor in parallel with the tantalum capacitor, the parallel ESR is relatively low. 

    3d. If 100kHz is the DS limit then I would stick with that. The chart referenced in the blog is to show an ESR comparison between different capacitor types. For the TPSM53603 case, you will be operating at 1.4MHz and the concern for MLCC ESR at low frequencies becomes trivial.

    4. The equation for UVLO is just a voltage divider equation to get enable voltage to the level to start switching of 1.23V. The equation is as shown below:

    • R_enb = 1.23V * (R_ent) / (Vin_uvlo - 1.23V) 

    Let me know if you need anything else.

    Regards,

    Jimmy

  • 0 in reply to Jimmy Hua
    Genius 4430 points

    Dear Jimmy,

    1)

    i'm looking at your equation for UVLO and it corresponds to the values in DS

    for 10V UVLO i get 100k for top and 14k for bottom resistor.

    But i also tried WEBENCH and when i enable UVLO voltage calculation and set it to 10V then the WEBENCH outputs for top resistor 100k and for bottom 732k ?? is there an error in WEBENCH?

    https://webench.ti.com/power-designer/switching-regulator/customize/271?AppType=None&Flavor=None&O1I=3&O1V=5&Topology=BUCK&VinMax=24.00&VinMin=12&VoltageOption=None&base_pn=TPSM53603&flavor=None&lang_chosen=en_US&op_TA=30&optfactor=3&origin=pf_panel

    2) the min Cin in Ds is specified as min ceramic 20uF

    2a) is this effective value with derating included ?

    2b) in the WEBENCH is showed only 2x 2.2uF GRM31CR61H225KA88L??

    Best Regards.

  • 0 in reply to d_zero
    TI__Mastermind 47060 points

    Hi,

    1.Thank you for bringing this to my attention. I have confirmed that the WEBENCH design is indeed showing a 100k top and 732k bottom which I will flag and immediately inform the WEBENCH support team.

    2a. The 20uF is a typical value from 2 x 10uF. I'd recommend using 1210 or 0805 case size ceramic capacitors for the input such that after 24V derating you still have some input capacitance.

    2b. Again I will inform the support team of this error. There must be some linking issue that resulted in this abnormally low input capacitor selection.

    Regards,

    Jimmy