This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

UCC23513: Evaluating UCC25313 with PSpice model for high side driver in high voltage regulator. Not going well.

Part Number: UCC23513
Other Parts Discussed in Thread: UCC27536, TPS40210

I get good results running a simulation of the UCC23513 as a stand alone part.

I can add a driven N-MOSFET also with good results. However, this in only the case when the source of the MOSFET is referenced to GND.

If I float the MOSFET above ground, providing Vcc via a bootstrapped supply referenced to Vss, the simulation fails.

I believe this is at least partly the result of the use of node 0 in nested sub circuits. Node 0 is always assumed by Spice to be ground.

My experience is the use of node 0 a model prevents it from operating in a floating application. I would love to be wrong here!

Please, tell me how to use your model in this fashion, or tell me the UCC23513, contrary to all indications in the data sheet, is not capable of operating in a floating configuration.

On the other hand, if the model is defective, please fix it! I'm nearing the point of doing a proof of performance board and I'm still in the dark regarding this part.


  • Hi, Thomas,

    Welcome to e2e, and sorry to hear of your difficulties.

    First, the UCC23513 absolutely can be used like you are trying to use it. As you suggested, this is an issue with the model.

    I don't see a reference to node 0 in the model, can you point out what you are seeing?

  • Hi Don,

    Thanks for the welcome. I've actually trolled here on and off for years but this is my first cry in the darkness. There actually appears to be a lot of light here!

    That's very good news about my hoped for usage of the  UCC23513, especially as I already have my procurement guy  getting parts for the prototypes!

    Node 0 is used in several of the nested (embedded) subcircuits.

    I don't have PSpice but, from experience, I trust TopSpices PSpice compatibility to be faithful in handling nested subcircuits just the same as OrCads program would.

    Altiums current simulation engine, on the other hand, takes all nested subcircuits and makes them global, which easily causes many a netlist to bomb.

    I do my schematic capture and netlist compilation in Altium and use TopSpice to run the generated netlist.  This combination has, so far, served well. On the other side, our PCB layout artist uses that part of Altium for his PCB work, and it does this quite well, so 2 for 3 with a good pinch hitter isn't too bad.

    To be fair, Altium is (finally) in the process of fixing & debugging many of the issues that have plagued their current simulator for several years. They have promised to keep at it with major enhancements in the next full release.

    Meanwhile, I'm struggling with TIs less than perfectly tested models. With the help of Penzar (TopSpice) I found and corrected syntax errors in the UCC27536 model. That one now runs.

    As long as I'm at it, I'll mention that the TPS40210 model is also litteerd with node 0 usage. This was common 10 to 20 years ago but since then most authors ceased the practice because it can be a real problem. The use of node 0 frequently prevents a model from working in a floating configuration.

    Tom Garson

    Aural Tech

  • Hi, Tom,

    Sorry, my team is only responsible for the UCC23513. If you have questions on other TI devices, please post a separate post, and the responsible team will respond.

    It's not clear to us - did you resolve the issue with the UCC23513 model on your own? Do you need further assistance from us?

  • Hi Don,

    I have not resolved the issues I am having with UCC25313 PSpice model.

    In order for me to move forward with my simulation, the model needs to be usable when the VSS terminal is not at ground potential. I believe this will require rebuilding the model without any internal connections to node 0.

    I understand that the physical part is not restricted to  use in a non floated application, but that leaves me in the less than comfortable position of having prototype PCBs produced without the assurance of a running simulation.

    I'm not a Spice Wizard by any means, although I gave correcting the model a try with only partial, unsatisfactory, results. It would be a major burden for me to continue to try to improve the model.

    While I'm not party to TIs internal processes for model creation, I would still be willing to assist in the process of correcting what I presently consider to be a significant deficiency in the model which renders it (the model) useless for the intended purpose.

    An easy way to test for this behavior is to create a circuit with a pulse generator driving anode to cathode. Connect Cathode to ground. Provide a positive voltage source (I use +24v) between VCC and VSS. Tie VSS to ground and you should observe proper activity at the output. Now, place a voltage source (say, +10v) between VSS and ground. My results are that output will be latched to the sum of both voltage sources.

    By the way, I peeked at you bio.

    PSU class of 73. We are.... First 2 years at Behrend in Erie. 1 year in State College. Did physics w/minor in EE. Left early to head to San Jose' to live while working at small lab in Mtn. View.

    Company I'm working with is Enervolt. Not allowed to say what I'm working on, but Enervolt is a promising startup looking to get big. Getting heat to have working prototype for upcoming presentation.

    Tom G

  • Hi, Tom,

    I'm going to ask my colleague to look into this model issue with you. Give us a couple days to look into this model issue.

    Wow! Small world! I have not been back on campus since I graduated as I moved to the West Coast after graduation.

  • Hi Don,

    I definitely appreciate that.

    If the model does work properly when tested with a recent release of PSpice, please let me know that, too.

    I use Penzars TopSpice, which has a strong focus on PSPice compatibility.

    Penzar has assured me that if I do run into a verified PSpice model which TopSpice can not handle, they will either update TopSpice to be able to use it, or rework the model so it will run in their environment.

    My fear is that OrCad has tinkered with PSpice to the point that they have broken some of the most fundamental rules of Berkeley Spice operation, possibly to make it extremely difficult for anyone to use even unencrypted PSpice models.

    I grew up about 90 miles east of State College and have been back to PA numerous times, but also have not actually been to University Park since the '70s.

  • Hi Tom, 

    I was working on this with Don.

    I ran some simulations in OrCad with our PSPICE model, both with UCC23513 floating on a DC voltage and with UCC23513 driving half bridge, with bootstrap.

    Both simulations ran fine and produced the correct results that we expect. 

    Below are some screencaps of plots showing the highside bias waveform. I had some issue with screencap not being able to display the connection so i drew the schematic.

    If you like, I can zip the OrCad projects up and post them here. They are based on the project included with the PSPICE models for this IC. 

    We see the correct bias in both (less bootstrap diode forward voltage in the half-bridge config)

    Below is the floating on DC voltage simulation, in this we are using large cap at VOUT. 

    This is the half bridge, note that it is using actual MOSFET model + bootstrap circuit.

    I can't see any issues with the model from our end in floating configuration. Like you said, it might be a good idea to reach out to Penzar. If you have any more questions on this topic please let us know. 



  • Well, it sure looks like the problem is at this end. My apologies for all the trouble.

    However, I still have to get to the bottom of it.

    If I run a sim with a purely capacitive load, output looks great up to about 10nF.

    It appears that the source of my difficulties comes from when I connect a MOSFET gate to the output of  the UCC23513.

    If you could post the OrCad projects you mention above, I can either run them directly or determine what MOSFETS are used.

    Thanks again.

  • Tom,

    It's no trouble. We're always happy to help.

    I used PSPICE nmos model in the half-bridge simulation, and 180nF cap load in the first simulation.

    Here are the projects:

    Original project (from

    Half bridge project below

    Floating w/ cap load below

    Please let us know if you need anything else, or have any other questions.



  • Hello Dimitri and Don,

    More fun with UCC25313...... However progress has been made.

    TopSpice is able to successfully run the test circuits you provided, as well as a larger portion of my own design, as long I use the default Spice NMOS model.

    However, I found that the stopper is when I try to incorporate the model for a recent Infineon CoolMOS device, the IPW60R0780P6, connecting its gate directly (via 68 ohm resistor) to the output of the UCC 25313.

    When I do this TopSpice does not converge.

    Next, comes the interesting part: If I insert a simpler, level 3, NMOS device ( STQ1NK60ZR-AP) between the UCC25313 and the IPW60R0780P6, the circuit converges with the expected  results. (It's plain from specifications that a physical UCC25313 should not require a buffer component to drive the Infineon device.)

    Please rerun your tests of the UCC25313 incorporating models of the above mentioned parts using PSpice and provide results. If you have no difficulties, I will pass the results on to Penzar to chew on.

    Thanks, again, for your help in this.

    Tom Garson

    For your convenience, I have pasted the models of those parts below:


    .SUBCKT IPW60R070P6_L0  drain  gate  source
    Lg     gate  g1    5n
    Ld     drain d1    3n
    Ls     source s1   5n
    Rs      s1    s2   2m

    Rg     g1    g2     1.04
    M1      d2    g2    s2    s2    DMOS    L=1u   W=1u
    .MODEL DMOS NMOS ( KP= 63.677  VTO=4.85  THETA=0  VMAX=1.5e5  ETA=0  LEVEL=3)
    Rd     d2    d1a    0.06 TC=10m
    .MODEL MVDR NMOS (KP=130.45 VTO=-1   LAMBDA=0.15)
    Mr d1 d2a d1a d1a MVDR W=1u L=1u
    Rx d2a d1a 1m
    Cds1 s2 d2 51.6p
    Dbd     s2    d2    Dbt
    .MODEL     Dbt    D(BV=600   M=0.9  CJO=45.09n  VJ=0.5V)
    Dbody   s2   21    DBODY
    .MODEL DBODY  D(IS=89905p  N=1.6  RS=4u  EG=1.12  TT=250n)
    Rdiode  d1  21    1.72m TC=3m

    .MODEL   sw    NMOS(VTO=0  KP=10   LEVEL=1)
    Maux      g2   c    a    a   sw
    Maux2     b    d    g2    g2   sw
    Eaux      c    a    d2    g2   1
    Eaux2     d    g2   d2    g2   -1
    Cox       b    d2   4.47n
    .MODEL     DGD    D(M=0.88   CJO=4.47n   VJ=0.5)
    Rpar      b    d2   1Meg
    Dgd       a    d2   DGD
    Rpar2     d2   a    10Meg
    Cgs     g2    s2    4.47n

    .ENDS  IPW60R070P6_L0


    *     Model Generated by STMicroelectronics         *
    *             All Rights Reserved               *
    *      Commercial Use or Resale Restricted          *
    * CREATION DATES: 17-11-2006                        *
    *                                                   *
    * POWER MOSFET Model (level 3)                      *
    *                                                   *
    * EXTERNAL PINS DESCRIPTION:                        *
    *                                                   *
    * PIN 1 -> Drain                                    *
    * PIN 2 -> Gate                                     *
    * PIN 3 -> Source                                   *
    *                                                   *
    *                    ****C****                      *
    *            **********************                 *
    *     ***************************************       *
    *              <<<<<<<<<<<>>>>>>>>>>>               *
    *     ***************************************       *
    *                                                   *
    .SUBCKT STQ1NK60ZR-AP 1 2 3
    LG 2 4  7.5E-09
    LS 12 3 7.5E-09
    LD 6 1  4.5E-09
    RG 4 5  9.947
    RS 9 12 0.919
    RD 7 6  10.052
    RJ 8 7  0.426E-01
    CGS 5 9   0.126E-09
    CGD 7 10  0.165E-09
    CK  11 7  0.948E-12
    DGD 11 7 DGD
    DBS 12 6 DBS
    DBD  9 7 DBD
    MOS  13 5 9 9 MOS L=1u W=1u
    E1  10 5 101 0 1
    E2  11 5 102 0 1
    E3  8 13 POLY(2) 6 8 6 12 0 0 0 0  0.299E-01
    G1  0 100 7 5 1u
    D1  100 101  DID
    D2  102 100  DID
    R1  101 0  1MEG
    R2  102 0  1MEG
    + LEVEL = 3
    + VTO   = 4.662
    + PHI   = 0.875
    + IS    = 0.1E-12
    + JS    = 0
    + THETA = 0.442E-01
    + KP    = 3.041
    + IS    = 0.1E-12
    + CJO   = 0.247E-10
    + VJ    = 0.781
    + M     = 0.293
    + IS    = 0.1E-12
    + CJO   = 0.551E-11
    + VJ    = 0.815
    + M     = 0.362
    + IS    = 0.1E-12
    + BV    = 625
    + N     = 1
    + TT    = 0.141E-06
    + RS    = 0.345E-02
    + IS    = 0.01E-12
    + RS    = 0
    + BV    = 635

  • Tom,

    I will run the simulations with these models and report back on our findings.

    In the meantime, could you first try to loosen your simulation parameters, specifically by increasing maximum step size and limiting TSTOP when driving IPW60R070P6  directly?

    This is from the app note included the IPW60R070P6 model. They point out potential issues with convergence.



  • Tom,

    I didn't have any problems running IPW60R070P6_L0 in simulation. Please see attached my settings and Schematic. Same as the floating test bench i showed earlier. I followed the recommended convergence settings from Infineon