LM26480-Q1: LM26480-Q1 nPOR & pool up resistor

nPOR has a VOL value specified on page 8 of the LM26480-Q1 datasheet:

Output level low (with load condition, IOL = 500 µA), VOL = 0.23 V typical, 0.5 V maximum.

If VIO = 3.3V, 3.3V/100kΩ = 33 µA, which is within the specification.

If VIO = 3.3V, 3.3V/10kΩ = 330 µA, which is also within the specification. It is OK to use a 10kΩ resistor,

Smallest resistor allowable (worst-case): 3.3V/500µA = 6.6 kΩ

Assuming the resistance through the FET is static, then Rds,on = 0.5V/500µA = 1 kΩ (max) then the time constant of discharge will be  = Rdson*C = (1 kΩ)*C and the time constant of charging will be  = Rpu*C where Rpu is the value of the pull-up resistor you have selected.

You will need to determine what is an acceptable rise time and fall time, which will determine the maximum capacitance you use for your EMI filter.

Florent,

For most I/Os, it is common to test the VOL (and VOH for push-pull outputs) by testing at the load current for which the I/O was designed to handle and measure the output voltage.

For this test, the nPOR signal is forced to pull low (regulated outputs not within regulation), which is the initial condition of this I/O. So during start-up, nPOR pin pulls low and a current source with Test Condition, IL = 500 µA, is applied at this pin. The source-meter will force 500 µA into the pin and measure the voltage. The voltage must be below 0.5V for the test to PASS. This ensures that the Rds,on of the internal open-drain FET is within spec and will pull low (VOL<0.5V) with the recommended pull-up resistor used.

It is not a measurement of the maximum load current, just a way to verify that VOL will be low enough to meet the target value. This measurement is to ensure Rds,on is low enough, but no one cares about the measured value of Rds,on. The only spec which matters is VOL, which must be lower than VIL for the input pin the nPOR connects to on the processor or other IC.

I am not concerned with 1.8mA going through the FET. Anything in the single-digit mA range is reasonable for an I/O pin.

Your only concern should be the timing of the RC constant and how that may impact your rise and fall times for the logic signal: Some logic inputs have a maximum slew rate. You want to make sure you do not violate this condition, if it is present in your system.

Florent,

Well, I2C is a good example, but not the problem you would face here: For I2C (or any other clocked communication protocol), the data must be valid before the data-valid clock edge (rising or falling), which is called the setup time. It must also be valid for a time period after the data-valid clock edge, which is called the hold time. If the pull-up resistors are too weak, or there is too much capacitance on the bus and a weak open-drain FET (high rds,on) then the rise or fall time for data may be too slow and it will not be ready when the data-valid clock pulse occurs (setup time violation).

It is difficult to think of another example, except for the most obvious one which is edge-triggered flip flops, a type of logic circuit that is notorious for creating race conditions. 

Put simply: unless the nPOR ouput pin of the LM26480-Q1 is tied directly to an nPOR input (or enable, EN) pin of another IC that is physically tied to the POR block in that IC, it would be a best practice to confirm that the other IC does not have any risk related to the slew rate of this signal.

Please keep in mind that this question is no longer related to the LM26480-Q1 device itself and there is very little TI can do to provide reassurance that the other IC at the other end of nPOR will behave as expected.