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UCC28780: About setting conditions of UCC28780

Part Number: UCC28780
Other Parts Discussed in Thread: LM5021

Hi, I am currently designing and using the UCC28780 circuit.

I use EXCEL design Calculator of the UCC28780.

For the following specifications, how should the condition be entered?

Condition : 85Vrms~276Vrms / 50Hz  、 30W/32V output (peak power : 200W、Assuming audio amp, load range is wide)

Could you tell me how to fill in Excel sheet C16 ~ C24?

Please tell us about the maximum duty.
Should the designer design the worst to be less than 0.5, just like a typical flyback?

(If the calculation result exceeds 0.5, should the specifications be reviewed?)

Could you give me an example of the transformer parameter entry on the calculation sheet?
If the input condition is set to the world wide specification (85Vrms ~ 276Vrms), it is troublesome because D-max exceeds 0.5.

  • Hello User4369382,

    Thank you for your interest in the UCC28780 ACF controller.

    Unfortunately, this device cannot support such a high peak to average power ratio.  Based on the over-power protection (OPP) threshold curve compared to the primary peak limit, the controller can support 0.8V/0.6V (133%) at the very lowest input and up to 0.8V/0.425V (188%) at high line. 

    So for a 30-W average power level, peak power is limited to 40W at 85Vac, and to 56.5W at 276Vac.  Conversely, for 200W peak power, the nominal power design point would have to be 150W, of which 30W is only 20% load.  Thermally, the power stage could be designed for steady-state losses from only 30W, but electrically, it would have to be designed as a 150-W converter.

    Running at D > 0.5 is not a concern, because this device operates in Transition Mode (TM) only.  There is no duty-cycle related stability issue for TM flyback, regardless of input voltage.

    For new ACF design, I recommend to obtain the latest Excel Calculator tool from our website, just recently updated: 

    Suggested inputs for your application at cells D16-D25 are:
    AC, 276, 230, 85, 80, 70, 47, 0.93

    If D30 = "30", then for 200W peak, D32 = "500" in order to set the OPP threshold at 150W to get the peak limit at 200W.  I have never used such a high pk/avg ratio before, so I do not know if the tool will work properly or fail at some calculation step due to some unknown limitation.

    If the UCC28780 cannot fulfil your needs and you must maintain 200W/30W, perhaps a controller capable of Continuous Conduction Mode (CCM) must be used, such as LM5021, to get the high peak power.  In the case of CCM, peak current-mode control with D > 0.5 will require slope compensation to maintain stability. LM5021 has that built-in.

    Regards,
    Ulrich

       

  • Hi, Ulrich

    Thanks for the great answer.
    I understand a lot.
    Also, the latest Excel tool is very easy to understand.
    (The previous version felt odd.)

    As your advice suggests, we will design it electrically at 200W. However, the thermal design should be 30W. (That is, thinning the wire system of the transformer, reducing the input capacitor, etc.)

    Please tell me two more points.

    1. Please tell me how to determine the switching frequency.

     (Formula or part constant setting method)

    I think that if the maximum frequency is designed at 400kHz , a transformer can be designed with the size of EI22.
    (It is designed not to saturate even at 200W, and it is equivalent to 50W thermally.)

    How can I determine the maximum frequency?
    How can the minimum frequency be determined?
    Please tell me the formula and the setting method in UCC28780.


    When calculated at 200 W (@ 160 kHz (min)) with the Excel tool, Lp was 24 uH.
    I think it's a bit too small, is it a reasonable number?
    Or if the minimum frequency is lowered to about 75kHz, it will be about 50uH.
    What are the recommended minimum and maximum frequencies?
    (Specification is 200W flyback. Thermal design is 30W)
    The core uses the equivalent in N49 from TDK. I want to try EER25 or EER22 because I want to make the size as small as possible)

    2. I am a SIMPLIS user. Therefore, I can run the UCC28780 simulation model that you created.
    How exactly does this model describe behavior?
    Can I operate in AAM, ABM, or LPM mode if I change the power supply voltage and load settings?
    Are other functions reproduced? (For example, protection circuit and start-up behavior)

    B.R. Tak

  • Hello Tak,

    I'm glad the latest calculator tool is easier to use.

    You mentioned "reducing the input capacitor" as part of the thermal design, but Cin must be sized for 200W, unfortunately, if the 200W must be delivered during the 160ms OPP interval.  Cin must still provide hold-up energy for 200W between each half-cycle peak of the lowest rated input voltage during this interval. Hundreds of switching cycles are processed at full power in each millisecond of operation and Cin cannot be undersized or Vout will fall out of regulation.       

    It is not easy to determine the maximum switching frequency.  In this ACF operation, maximum frequency is a function of output power, primary inductance and the amount of negative current needed to achieve ZVS at high line, as seen in Equation 29 in the datasheet.  To use this, all of the factors must be chosen first.

    Lm is determined based on the minimum switching frequency targeted by the user. The frequency at any other operating point cannot be determined until after the minimum is selected. The guideline for choosing fSW(min) is vague, though, based on balancing user goals with reality checks. For example, driving frequency higher is generally expected to drive transformer size down (preferably to zero).  However, the UCC28780 propagation delays will begin to affect operation above ~1Mhz, and ferrite core materials for higher frequencies become more difficult to get, Rac effects are larger, gate-drive bias currents are higher, Si-Fets can't support that rate, pcb layout becomes critical for low EMI and parasitics, etc.      
    One may expect fSW(max) to typically be 2~3X fSW(min).  (It is not a fixed ratio.)

    24uH seems low, but is not unreasonable considering that Lm is calculated to allow the peak current necessary for 200W to build up at the minimum bulk voltage and demagnetize at 30V within the 6.25us period. However, placing "200" in Cell D30 is too much overdesign.  You will get a 267W OPP level.
    Instead, I suggest to set D30 to 136.4W and D30 to 110%, and 200W will automatically be the max power available, for 160ms.  This, plus setting Nps = 4, raises Lm to 39uH.

    Concerning the SIMPLIS model: there are application notes on the model's schematic page that list the conditions for which the model is not valid. I believe fault-modes are modeled. The full AAM-ABM-LP-SBP operating range is modeled.  Start-up is abbreviated and input is DC to speed up simulation, but these simplifications can be changed by the user to include AC rectification and bulk capacitance and VDD charge-up.  However simulation time will be greatly increased.  

    Regards,
    Ulrich

     

  • Hi, Ulrich

    Thank you for great support !

    Your advice solved a lot of my troubles. It seems that we can make prototypes with a lot of confidence.

    I will try the design of the transformer with the setting value you recommended (Nps: 4, around 39uH). Also, if I have any questions, I will post. The lowest frequency should be 160kHz and the input capacitor should be a little larger. I will design the leakage inductance to be 2.5uH.
    I have one more question. Is synchronous rectification better on the secondary side? Is asynchronous rectification a disadvantage?
    Because the current value is not so large.
    Since it is an active clamp and boundary mode, I think that synchronous rectification is easy to realize, but I do not know the effect (benefit).
    For comparison, a 200V high performance FET is ready to be implemented.
    Is an LC filter (including damping filter) required?
    (1uH and 0.68uH ESR 200mΩ)
    I think it is unnecessary when trying with asynchronous rectification.
    As a result, why not downsizing and cost reduction?

    Please tell me how to select synchronous rectification or asynchronous rectification.
    I'm wondering which is better. (When judged in terms of cost, size, efficiency, noise, etc.)

    B.R.Tak

  • Hello Tak,

    Asynchronous rectification is basically just a diode on the output, while synchronous rectification (SR) uses a MOSFET to reduce the forward voltage drop of the rectifier.  The main benefit of SR is to minimize the rectification loss and improve overall efficiency.

    SR provides a great benefit for low voltage outputs, but less so at higher voltages. For example, with Diode VF = 0.5V at 5V output, this represents a loss of ~10% of the output power.    With SR drop of 0.05V, this becomes only ~1% loss. 

    For a Vout = 32V, an SR Fet will still reduce the loss compared to a diode, but the improvement will be a smaller percentage of the overall losses. It becomes an economic  tradeoff of whether the small efficiency improvement is worth the extra expense and complication of the SR Fet+control+bias network.  There is no sharp boundary between where SR is worth it and where SR is not worth it.  The decision is very clear at low voltages, and becomes more and more "foggy" as Vout increases.  For reference, though, SR is used for 20V outputs in USB-PD charger designs which require very dense packaging.  They need the least loss possible to minimize internal temperature rise.

    The LC filter is not necessary, but can have 2 major functions, which are different in ACF. 

    The first is the traditional high-frequency noise filter where a small L and small C are added to the output of a large output capacitor to minimize switching ripple voltage. Here, no damping is required.

    The second is more complicated, but the LC is not a noise filter.  Instead, it is used to change the ACF mode from primary-side resonance to secondary-side resonance.  Please refer to Section 8.2.2.3 of the UCC28780 datasheet page 41 for more details on this.  This s a different L-C arrangement that helps improve efficiency by changing the resonance mode, but it also introduces more complication.  In this case, too, the parallel damping L helps avoid unwanted resonance to maintain stability while in burst mode.   An SR-Fet can be used with secondary-resonance, but is not required.  A diode can be used, too, with no problem.  With secondary-resonance, the damping-L is beneficial regardless of whether SR or diode is used.  

    Both the SR and the LC arrangement are economic decisions, depending on the packaging and loss targets of your design.

    Regards,
    Ulrich

  • Hi , Ulrich

    Thank you for the wonderful commentary.
    I was able to understand very deeply.
    The first trial implements synchronous rectification and LC filter.
    Then, clarify pros and cons and make a final decision.

    Thank you very much.

    B.R. Tak